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nak: fix MMA latencies on Ampere
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Fixes: 7a01953a39 ("nak: Add Ampere and Ada latency information")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37941>
This commit is contained in:
Karol Herbst
Marge Bot
parent
cf4df97093
commit
e7dca5a6ca
1 changed files with 56 additions and 33 deletions
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@ -602,8 +602,9 @@ impl RegLatencySM80 {
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| FP16 | FP16_Alu | FP16_F32 => 1,
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 3, 3),
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Clmad => pred(has_pred, 5, 3),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 8, 1),
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MMA_2x_collect => pred(has_pred, 12, 1),
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IMMA_88 => pred(has_pred, 8, 1),
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MMA_1x_collect => pred(has_pred, 11, 1),
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MMA_2x_collect => pred(has_pred, 19, 1),
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DMMA => pred(has_pred, 20, 1),
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Cbu => 1,
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Decoupled => 1,
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@ -617,8 +618,9 @@ impl RegLatencySM80 {
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 => 1,
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 3, 1),
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Clmad => pred(has_pred, 5, 1),
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IMMA_88 | MMA_1x_collect => 8,
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MMA_2x_collect => 12,
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IMMA_88 => 8,
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MMA_1x_collect => 11,
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MMA_2x_collect => 19,
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DMMA => 20,
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Cbu => 1,
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Decoupled => 1,
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@ -634,8 +636,9 @@ impl RegLatencySM80 {
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IMADWideWriteDH => pred(has_pred, 1, 1),
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 3, 3),
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Clmad => pred(has_pred, 5, 3),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 8, 1),
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MMA_2x_collect => pred(has_pred, 12, 1),
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IMMA_88 => pred(has_pred, 8, 1),
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MMA_1x_collect => pred(has_pred, 11, 1),
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MMA_2x_collect => pred(has_pred, 19, 1),
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DMMA => pred(has_pred, 20, 1),
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Cbu => 1,
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Decoupled => 1,
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@ -653,8 +656,9 @@ impl RegLatencySM80 {
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FP16 | FP16_Alu | FP16_F32 => pred(has_pred, 1, 2),
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 5, 3),
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Clmad => pred(has_pred, 5, 5),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 8, 3),
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MMA_2x_collect => pred(has_pred, 12, 3),
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IMMA_88 => pred(has_pred, 8, 3),
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MMA_1x_collect => pred(has_pred, 11, 3),
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MMA_2x_collect => pred(has_pred, 19, 3),
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DMMA => pred(has_pred, 20, 3),
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Cbu => 1,
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Decoupled => 1,
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@ -671,8 +675,9 @@ impl RegLatencySM80 {
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| FP16_F32 => 1,
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 5, 1),
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Clmad => pred(has_pred, 5, 3),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 8, 1),
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MMA_2x_collect => pred(has_pred, 12, 1),
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IMMA_88 => pred(has_pred, 8, 1),
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MMA_1x_collect => pred(has_pred, 11, 1),
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MMA_2x_collect => pred(has_pred, 19, 1),
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DMMA => pred(has_pred, 20, 1),
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Cbu => 1,
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Decoupled => 1,
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@ -689,8 +694,9 @@ impl RegLatencySM80 {
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| FP16_F32 => 1,
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 3, 3),
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Clmad => pred(has_pred, 5, 3),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 8, 1),
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MMA_2x_collect => pred(has_pred, 12, 1),
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IMMA_88 => pred(has_pred, 8, 1),
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MMA_1x_collect => pred(has_pred, 11, 1),
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MMA_2x_collect => pred(has_pred, 19, 1),
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DMMA => pred(has_pred, 20, 1),
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Cbu => 1,
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Decoupled => 1,
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@ -704,8 +710,9 @@ impl RegLatencySM80 {
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 => 1,
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 3, 2),
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Clmad => pred(has_pred, 5, 2),
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IMMA_88 | MMA_1x_collect => 8,
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MMA_2x_collect => 12,
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IMMA_88 => 8,
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MMA_1x_collect => 11,
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MMA_2x_collect => 19,
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DMMA => 20,
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Cbu => 1,
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Decoupled => 1,
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@ -720,8 +727,9 @@ impl RegLatencySM80 {
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HFMA2_MMA => 2,
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RedirectedFP64 => 3,
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Clmad => pred(has_pred, 5, 1),
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IMMA_88 | MMA_1x_collect => 8,
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MMA_2x_collect => 12,
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IMMA_88 => 8,
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MMA_1x_collect => 11,
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MMA_2x_collect => 19,
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DMMA => 20,
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Cbu => 1,
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Decoupled => 1,
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@ -736,8 +744,9 @@ impl RegLatencySM80 {
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HFMA2_MMA => 2,
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RedirectedFP64 => 2,
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Clmad => pred(has_pred, 4, 2),
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IMMA_88 | MMA_1x_collect => 7,
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MMA_2x_collect => 11,
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IMMA_88 => 7,
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MMA_1x_collect => 10,
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MMA_2x_collect => 18,
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DMMA => 19,
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Cbu => 1,
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Decoupled => 1,
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@ -750,8 +759,9 @@ impl RegLatencySM80 {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideWriteDL
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 | HFMA2_MMA
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| RedirectedFP64 | Clmad => 2,
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IMMA_88 | MMA_1x_collect => 7,
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MMA_2x_collect => 11,
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IMMA_88 => 7,
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MMA_1x_collect => 10,
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MMA_2x_collect => 18,
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DMMA => 19,
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Cbu => 1,
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Decoupled => 1,
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@ -764,8 +774,9 @@ impl RegLatencySM80 {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideWriteDL
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 | HFMA2_MMA
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| RedirectedFP64 | Clmad => 2,
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IMMA_88 | MMA_1x_collect => 4,
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MMA_2x_collect => 8,
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IMMA_88 => 4,
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MMA_1x_collect => 8,
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MMA_2x_collect => 16,
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DMMA => 17,
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Cbu => 1,
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Decoupled => 1,
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@ -778,8 +789,9 @@ impl RegLatencySM80 {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideWriteDL
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 | HFMA2_MMA
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| RedirectedFP64 | Clmad => 2,
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IMMA_88 | MMA_1x_collect => 4,
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MMA_2x_collect => 8,
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IMMA_88 => 4,
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MMA_1x_collect => 8,
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MMA_2x_collect => 16,
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DMMA => 16,
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Cbu => 1,
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Decoupled => 1,
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@ -795,8 +807,9 @@ impl RegLatencySM80 {
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}
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HFMA2_MMA | RedirectedFP64 => pred(has_pred, 1, 9),
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Clmad => pred(has_pred, 1, 11),
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IMMA_88 | MMA_1x_collect => pred(has_pred, 7, 6),
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MMA_2x_collect => pred(has_pred, 11, 6),
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IMMA_88 => pred(has_pred, 7, 6),
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MMA_1x_collect => pred(has_pred, 10, 5),
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MMA_2x_collect => pred(has_pred, 18, 5),
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DMMA => pred(has_pred, 19, 6),
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Cbu => 1,
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Decoupled => 1,
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@ -815,15 +828,25 @@ impl RegLatencySM80 {
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use RegLatencySM80::*;
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match writer {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideWriteDL
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 | HFMA2_MMA
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| RedirectedFP64 => match reader {
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MMA_2x_collect => 7,
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_ => 1,
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},
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Clmad | IMMA_88 | MMA_1x_collect | MMA_2x_collect | DMMA | Cbu
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| IMADWideWriteDH | FP16 | FP16_Alu | FP16_F32 | HFMA2_MMA => {
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match reader {
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MMA_2x_collect => 7,
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_ => 1,
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}
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}
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RedirectedFP64 => 1,
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Clmad | IMMA_88 | MMA_1x_collect | MMA_2x_collect | DMMA
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| Decoupled | DecoupledAgu => match reader {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideReadAB
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| IMADWideReadCL | IMADWideReadCH => 2,
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| IMADWideReadCL | IMADWideReadCH | FP16 | FP16_Alu
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| FP16_F32 | HFMA2_MMA => 2,
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_ => 1,
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},
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Cbu => match reader {
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CoupledAlu | CoupledDisp64 | CoupledFMA | IMADWideReadAB
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| IMADWideReadCL | IMADWideReadCH | FP16 | FP16_Alu
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| FP16_F32 | HFMA2_MMA => 2,
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MMA_2x_collect => 7,
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_ => 1,
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},
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_ => {
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