Commit graph

21826 commits

Author SHA1 Message Date
Chia-I Wu
45cbc9267e ilo: rename ILO_DEBUG=3d
It has been a bad name since we added the builder.  Rename it to
ILO_DEBUG=batch to match i965, and call ilo_builder_decode() from
ilo_cp_submit_internal().
2014-09-19 16:02:11 +08:00
Chia-I Wu
8a2352262e ilo: rename ilo_cp_flush()
"Flush" is used for too many things already: pipe resource flush, pipe context
flush, pipe transfer region flush, and hardware pipeline flush.  Rename it to
ilo_cp_submit().  As such, ILO_DEBUG=flush is renamed to ILO_DEBUG=submit.
2014-09-19 16:02:11 +08:00
Chia-I Wu
1887d15eed ilo: remove ilo_cp_empty()
Call ilo_builder_batch_used() directly.
2014-09-19 16:02:11 +08:00
Chia-I Wu
270667472f ilo: simplify ilo_cp_set_owner()
The simplification allows us to get rid of ilo_cp_set_ring() and
ilo_cp_implicit_flush().  The 3D query code is refactored for the
simplification.
2014-09-19 16:02:11 +08:00
Eric Anholt
19589147ef vc4: Add support for stencil operations.
While depth test state is passed through the fragment shader as sideband,
data, the stencil test state has to be set by the fragment shader itself.

Many tests are still failing, but this gets most of hiz/ passing.
2014-09-18 17:46:43 -07:00
Eric Anholt
6e39854e23 vc4: Actually implement VC4_DEBUG=cl. 2014-09-18 11:46:50 -07:00
Roland Scheidegger
019ca99bee draw: (trivial) remove duplicated lines 2014-09-18 16:13:24 +02:00
Eric Anholt
71d4fc88d6 vc4: Allow copy propagation of uniforms.
Fixes 12 piglit tests (and 8 more crash -> fail) from reducing register
pressure.
2014-09-17 14:21:24 -07:00
Eric Anholt
79be2cc383 vc4: Make sure thread end doesn't have a uniform read.
Prevents regression when I start doing copy propagation on uniforms.
2014-09-17 14:21:24 -07:00
Eric Anholt
44b8eb743d vc4: Allow dead code elimination of instructions that read uniforms. 2014-09-17 14:21:24 -07:00
Eric Anholt
5e90ed79f6 vc4: Add support for reordering the uniform stream after optimization.
This allows for introducing dead code eliminating of uniforms, copy
propagation of uniforms, and instruction rescheduling between instructions
that both read uniforms.
2014-09-17 14:21:24 -07:00
Eric Anholt
b0256fb75f vc4: Initialize the various qreg arrays when allocating them.
This is particularly important for outputs, where we try to MOV the whole
vec4 to the VPM, even if only 1-3 components had been set up.  It might
also be important for temporaries, if the shader reads components before
writing them.
2014-09-17 14:21:24 -07:00
Eric Anholt
b44a7a3223 vc4: Fix stray disable of the CSE pass.
Somehow I slipped this in with the original commit of CSE.
2014-09-17 14:21:24 -07:00
rconde
ffeb77c7b0 gallivm,tgsi: fix idiv by zero crash
While the result of signed integer division by zero is undefined by glsl
(and doesn't exist with d3d10), we must not crash, so need to make sure we
don't get sigfpe much like udiv already does.
Unlike udiv where we return 0xffffffff (as required by d3d10) there is
no requirement right now to return anything specific so we use zero.
2014-09-17 18:31:54 +02:00
Roland Scheidegger
4d996877ca gallivm: add texture target information for sample opcodes to tgsi info
sample opcodes don't have valid texture target information (and I don't think
this should be changed), however it would be nice if we had that information
ready elsewhere, so stuff that information into the tgsi info when analyzing
a shader.

v2: Ilja Mirkin spotted some bugs wrt not handling msaa resources. So add them
and while there also add them to the tex opcode analysis this was cloned from
as well (plus get rid of some bug not detecting indirect textures there in some
cases too).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-09-17 18:31:54 +02:00
Richard Sandiford
234d194b49 gallium: Define PIPE_FORMAT_xyzw8888_{SNORM, SRGB} aliases
...i.e. formats in which the first listed component is in the least
significant byte of the integer.  The corresponding UNORM aliases already exist.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-17 13:17:46 +10:00
Richard Sandiford
f9d8574b5e gallium: Add PIPE_FORMAT_x8B8G8R8_SNORM formats
This means that each RnGnBnxn format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.
The associated UNORM and SRGB formats already exist.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-17 13:17:46 +10:00
Richard Sandiford
9b4c13995c gallium: Define PIPE_FORMAT_{LA, AL, RG, GR}nn aliases
...i.e. formats in which the first listed component is in the least
significant half of the integer.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-17 13:17:46 +10:00
Richard Sandiford
f14b40ab32 gallium: Add PIPE_FORMAT_AnLn and PIPE_FORMAT_GnRn formats
...i.e. formats in which the alpha or green channel is first in memory.

This means that each LnAn and RnGn format has a reversed counterpart,
which is necessary for handling big-endian mesa<->gallium mappings.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-17 13:17:46 +10:00
Dave Airlie
ebcb2ee989 util: move shared rgtc code to util (v2)
This was being shared using a ../../ get out of gallium into
mesa, and I swore when I did it I'd fix things when we got a util
dir, we did, so I have.

v2: move RGTC_DEBUG define

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-17 11:27:25 +10:00
Eric Anholt
2b6711cc5f vc4: Claim ARB_fbo.
This gets a ton of piglit working that crashes in waffle context
management stuff otherwise.  Actually supporting mismatched FB sizes is at
best going to require some more load/store generals for color buffers, but
if I can't manage to do that I'll want to just have state_tracker reject
those FBOs as unsupported, rather than deny GL 2.1.
2014-09-16 15:14:52 -07:00
Eric Anholt
3c6d85e725 vc4: Fix memory leaks in register allocation. 2014-09-16 15:14:52 -07:00
Eric Anholt
ad02ba42f0 vc4: Move register allocation to a separate file.
I'm going to be rewriting it all, and having it mixed up with the
QIR-to-QPU opcode translation was messy.
2014-09-16 15:14:52 -07:00
Eric Anholt
2264925f85 vc4: Add support for computed depth writes.
Fixes piglit glsl-1.10-fragdepth and early-z.
2014-09-16 13:03:41 -07:00
Eric Anholt
aae4223fbd vc4: Restructure depth input/output in fragment shaders.
The goal here is to have an argument for the depth write opcode so that I
can do computed depth.  In the process, this makes the calculations that
will be emitted more obvious in the QIR.
2014-09-16 13:03:32 -07:00
Ilia Mirkin
a420aa1b41 freedreno: add a standalone ir3_compiler binary for building TGSI
Compiler taken from the combo old/new compiler comparer + simulator.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-09-16 12:13:22 -04:00
Ilia Mirkin
5b1d316c51 freedreno: add default .dir-locals.el for emacs settings
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-09-16 12:13:22 -04:00
Dave Airlie
8de5522d93 llvmpipe: fix rast debugging output
The triangle_32_ rast functions never made it into the debug output,
confused me for a few seconds.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-16 15:12:54 +10:00
Richard Sandiford
f93b6d8cc5 util: Add big-endian layout for a number of formats.
This patch builds on 6c8f547f66 and
previous patches by allowing u_format.csv to specify separate big-endian
and little-endian layouts.  It then uses this to specify the correct layouts
for various depth/stencil formats.  Later patches handle other formats.

To recap, the idea is that u_format.csv lists the channels for an N-byte
value as though it were an N-byte integer.  For little-endian targets
the channels are listed starting at the least-significant bit of the
integer while for big-endian targets the channels are listed starting
at the most-significant bit.  This means that for something like
PIPE_FORMAT_B8G8R8A8_UNORM (blue in first byte of memory, alpha in last
byte of memory) the orders are the same for both endiannesses.  But for
something like PIPE_FORMAT_S8_UINT_Z24_UNORM, where the stencil is in
the least significant byte of a 32-bit integer, there need to be separate
channel definitions for each endianness.

The effect of this patch is to make the affected PIPE_FORMAT_*s have
the same layout as the associated MESA_FORMAT_*s for big-endian.
The MESA_FORMAT_*s are already handled correctly.

Fixes various piglit tests on z.  No regressions on x86_64.

[airlied: squash subsequent patches]
util: Add big-endian layout for 5551 and 565 formats
util: Add big-endian layout for 10/10/10/2 formats
util: Add big-endian layout for 4444 formats
util: Add big-endian layout for 233 format
util: Add big-endian layout for 44 formats

Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-16 14:02:56 +10:00
Richard Sandiford
9cd4dced06 llvmpipe: Fix PIPE_FORMAT_Z32_FLOAT_S8X24_UINT handling for big-endian.
llvmpipe treats PIPE_FORMAT_Z32_FLOAT_S8X24_UINT as a bit of a special case,
handling it as two 32-bit pieces rather than a single 64-bit block:

   /* 64bit d/s format is special already extracted 32 bits */
   total_bits = format_desc->block.bits > 32 ? 32 : format_desc->block.bits;

The format_desc describes the whole 64-bit block, so the z shift
will be 32 for big-endian.  But since we're accessing the z channel
as a 32-bit value rather than a 64-bit value, we need to mask the shift
with 31.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-16 14:02:55 +10:00
Richard Sandiford
1a65629ccc gallivm: Fix uses of 2^24
Fallback cases in lp_bld_arit.c used 2^24 to mean "2 to the power 24",
but in C it's "2 xor 24", i.e. 26.  Fixed by using 1<< instead.

Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: "10.2 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-09-16 14:02:55 +10:00
Richard Sandiford
0a7f9fe42b gallivm: Add SNORM clamping to lp_build_{add, sub}
...fixing the associated TODO.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com>
2014-09-16 14:02:54 +10:00
Rafael Ávila de Espíndola
f6e71ff9eb gallivm: attach DataLayout to module too, not just pass manager.
It looks like it was possible to attach it to both for a long time, however
since llvm r217548 attaching it to just the pass manager is no longer
sufficient and causes bugs (see http://llvm.org/bugs/show_bug.cgi?id=20903).

Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-09-16 03:50:32 +02:00
Roland Scheidegger
145fef9636 gallivm: handle SAMPLE opcode in aos sampling
This is just a very limited version, in particular sampler and sampler view
index must be the same. It cannot handle any modifiers neither.
Works much the same as soa version otherwise, to figure out the target we
need to store the sampler view dcls.
While here, also handle (no-op) RET and get rid of a couple bogus deprecated
comments.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-09-16 03:50:31 +02:00
Roland Scheidegger
02595c55b0 tgsi: accept offsets for sample opcodes too in the text parser
sample opcodes are a little oddly represented in the opcode_info, since
they don't count as texture instructions - they don't have valid target
information, but they may have offsets (unlike "ordinary" texture
instructions, the texture token may be optional for them).
So just make sure with these opcodes the optional offsets are accepted.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-09-16 03:50:31 +02:00
Roland Scheidegger
3a9eb40ee1 tgsi: don't print texture target for sample opcodes
sample opcodes don't encode a texture target, it would thus always
print UNKNOWN, which is not helpful (and wouldn't parse when giving
back the shader text to tgsi).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-09-16 03:50:31 +02:00
Eric Anholt
84ca6bc113 vc4: Bump maximum ARB program temporaries to match Intel/AMD.
This query has always been useless, but we could potentially reject
well-formed, runnable programs if we expose a value that's too low.
2014-09-15 15:05:06 -07:00
Eric Anholt
33443f506f vc4: Bump maximum uniforms count to match other drivers.
We don't have any specific limits in the hardware, just like the other
GPUs, so match their behavior.  Fixes minmax_gles2 and several other
piglit tests relying on the specced uniform minmax values.
2014-09-15 15:04:38 -07:00
Eric Anholt
5638b87d4c vc4: Dynamically allocate the TGSI-to-qreg arrays.
Fixes buffer overflows in some piglit tests (which are still failing to
register allocate anyway).
2014-09-15 13:12:27 -07:00
Eric Anholt
2147dd9681 vc4: Fix memory leaks of struct qinst. 2014-09-15 13:12:27 -07:00
Eric Anholt
f78ee1b280 vc4: Fix memory leaks of some vc4_compile contents. 2014-09-15 13:12:27 -07:00
Eric Anholt
50292d76c5 vc4: Reuse the util header instead of defining our own ARRAY_SIZE.
Fixes redefinition warnings if you end up including this header before
util stuff.
2014-09-15 13:12:27 -07:00
Chia-I Wu
ce50a61d36 ilo: clean up 3D/media functions
Mostly style changes to set dw[0] directly.
2014-09-15 10:25:35 +08:00
Chia-I Wu
c39377d3fc ilo: fix gen6_3DSTATE_MULTISAMPLE()
There was a typo introduced by 90f4b131fc.
2014-09-15 09:00:54 +08:00
Rob Clark
ca29c4c3b0 freedreno/a3xx: 3d/array textures
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-13 15:31:58 -04:00
Rob Clark
eea1cdf687 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-09-13 15:31:58 -04:00
Chia-I Wu
a32f48361a ilo: trust vertex element count more
We might run into ve->count == 0 and last_velement_edgeflag == true in
gen6_3DSTATE_VERTEX_ELEMENTS() when the state tracker sets an invalid
combination of VS and VE (does not seem to happen with st/mesa).  Do not
assume ve->count is positive when last_velement_edgeflag is true.

Reported by Coverity.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-14 00:30:33 +08:00
Chia-I Wu
8fcf1b1f90 ilo: simplify src operand gathering in disassembler
Always initialize the operand array to point to src0, src1, and src2.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-14 00:30:33 +08:00
Chia-I Wu
5341001b94 ilo: derive 3-src instructions from the opcode table
One less switch statement to maintain.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-09-14 00:30:33 +08:00
Chia-I Wu
9133784a46 ilo: clean up 3DPRIMITIVE functions
Add ILO_PRIM_RECTANGLES to replace the rectlist bool.
2014-09-13 09:33:20 +08:00