mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 16:08:04 +02:00
vc4: Move register allocation to a separate file.
I'm going to be rewriting it all, and having it mixed up with the QIR-to-QPU opcode translation was messy.
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commit
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4 changed files with 165 additions and 100 deletions
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@ -23,6 +23,7 @@ C_SOURCES := \
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vc4_qpu_emit.c \
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vc4_qpu.h \
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vc4_qpu_validate.c \
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vc4_register_allocate.c \
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vc4_resource.c \
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vc4_resource.h \
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vc4_screen.c \
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@ -230,6 +230,7 @@ void vc4_flush(struct pipe_context *pctx);
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void vc4_flush_for_bo(struct pipe_context *pctx, struct vc4_bo *bo);
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void vc4_emit_state(struct pipe_context *pctx);
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void vc4_generate_code(struct vc4_compile *c);
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struct qpu_reg *vc4_register_allocate(struct vc4_compile *c);
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void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
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bool vc4_rt_format_supported(enum pipe_format f);
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@ -210,43 +210,11 @@ serialize_insts(struct vc4_compile *c)
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void
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vc4_generate_code(struct vc4_compile *c)
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{
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struct qpu_reg allocate_to_qpu_reg[4 + 32 + 32];
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bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
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int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
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int *reg_uses_remaining =
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calloc(c->num_temps, sizeof(*reg_uses_remaining));
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struct qpu_reg *temp_registers = vc4_register_allocate(c);
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bool discard = false;
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for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++)
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reg_in_use[i] = false;
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for (int i = 0; i < c->num_temps; i++)
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reg_allocated[i] = -1;
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uint32_t next_reg = 0;
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for (int i = 0; i < 4; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_rn(i == 3 ? 4 : i);
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for (int i = 0; i < 32; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_ra(i);
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for (int i = 0; i < 32; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_rb(i);
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assert(next_reg == ARRAY_SIZE(allocate_to_qpu_reg));
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make_empty_list(&c->qpu_inst_list);
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struct simple_node *node;
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foreach(node, &c->instructions) {
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struct qinst *qinst = (struct qinst *)node;
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if (qinst->dst.file == QFILE_TEMP)
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reg_uses_remaining[qinst->dst.index]++;
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for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
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if (qinst->src[i].file == QFILE_TEMP)
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reg_uses_remaining[qinst->src[i].index]++;
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}
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if (qinst->op == QOP_FRAG_Z)
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reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
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}
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switch (c->stage) {
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case QSTAGE_VERT:
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case QSTAGE_COORD:
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@ -259,6 +227,7 @@ vc4_generate_code(struct vc4_compile *c)
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break;
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}
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struct simple_node *node;
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foreach(node, &c->instructions) {
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struct qinst *qinst = (struct qinst *)node;
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@ -306,18 +275,7 @@ vc4_generate_code(struct vc4_compile *c)
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src[i] = qpu_rn(0);
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break;
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case QFILE_TEMP:
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if (reg_allocated[index] == -1) {
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fprintf(stderr, "undefined reg use: ");
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qir_dump_inst(qinst);
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fprintf(stderr, "\n");
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src[i] = qpu_rn(0);
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} else {
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src[i] = allocate_to_qpu_reg[reg_allocated[index]];
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reg_uses_remaining[index]--;
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if (reg_uses_remaining[index] == 0)
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reg_in_use[reg_allocated[index]] = false;
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}
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src[i] = temp_registers[index];
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break;
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case QFILE_UNIF:
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src[i] = qpu_unif();
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@ -333,63 +291,9 @@ vc4_generate_code(struct vc4_compile *c)
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case QFILE_NULL:
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dst = qpu_ra(QPU_W_NOP);
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break;
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case QFILE_TEMP:
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if (reg_allocated[qinst->dst.index] == -1) {
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int alloc;
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for (alloc = 0;
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alloc < ARRAY_SIZE(reg_in_use);
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alloc++) {
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struct qpu_reg reg = allocate_to_qpu_reg[alloc];
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switch (qinst->op) {
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case QOP_PACK_SCALED:
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/* The pack flags require an
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* A-file register.
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*/
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if (reg.mux != QPU_MUX_A)
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continue;
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break;
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case QOP_TEX_RESULT:
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case QOP_TLB_COLOR_READ:
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/* Only R4-generating
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* instructions get to store
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* values in R4 for now, until
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* we figure out how to do
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* interference.
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*/
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if (reg.mux != QPU_MUX_R4)
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continue;
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break;
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case QOP_FRAG_Z:
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if (reg.mux != QPU_MUX_B ||
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reg.addr != QPU_R_FRAG_PAYLOAD_ZW) {
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continue;
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}
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break;
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default:
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if (reg.mux == QPU_MUX_R4)
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continue;
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break;
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}
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if (!reg_in_use[alloc])
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break;
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}
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assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc");
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reg_in_use[alloc] = true;
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reg_allocated[qinst->dst.index] = alloc;
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}
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dst = allocate_to_qpu_reg[reg_allocated[qinst->dst.index]];
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reg_uses_remaining[qinst->dst.index]--;
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if (reg_uses_remaining[qinst->dst.index] == 0) {
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reg_in_use[reg_allocated[qinst->dst.index]] =
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false;
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}
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dst = temp_registers[qinst->dst.index];
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break;
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case QFILE_VARY:
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case QFILE_UNIF:
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assert(!"not reached");
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@ -645,4 +549,6 @@ vc4_generate_code(struct vc4_compile *c)
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vc4_dump_program(c);
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vc4_qpu_validate(c->qpu_insts, c->qpu_inst_count);
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free(temp_registers);
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}
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157
src/gallium/drivers/vc4/vc4_register_allocate.c
Normal file
157
src/gallium/drivers/vc4/vc4_register_allocate.c
Normal file
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@ -0,0 +1,157 @@
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/*
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* Copyright © 2014 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <inttypes.h>
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#include "vc4_context.h"
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#include "vc4_qir.h"
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#include "vc4_qpu.h"
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/**
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* Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
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*
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* The return value should be freed by the caller.
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*/
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struct qpu_reg *
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vc4_register_allocate(struct vc4_compile *c)
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{
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struct simple_node *node;
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struct qpu_reg allocate_to_qpu_reg[4 + 32 + 32];
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bool reg_in_use[ARRAY_SIZE(allocate_to_qpu_reg)];
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int *reg_allocated = calloc(c->num_temps, sizeof(*reg_allocated));
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int *reg_uses_remaining =
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calloc(c->num_temps, sizeof(*reg_uses_remaining));
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struct qpu_reg *temp_registers = calloc(c->num_temps,
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sizeof(*temp_registers));
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for (int i = 0; i < ARRAY_SIZE(reg_in_use); i++)
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reg_in_use[i] = false;
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for (int i = 0; i < c->num_temps; i++)
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reg_allocated[i] = -1;
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/* If things aren't ever written (undefined values), just read from
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* r0.
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*/
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for (int i = 0; i < c->num_temps; i++)
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temp_registers[i] = qpu_rn(0);
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uint32_t next_reg = 0;
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for (int i = 0; i < 4; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_rn(i == 3 ? 4 : i);
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for (int i = 0; i < 32; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_ra(i);
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for (int i = 0; i < 32; i++)
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allocate_to_qpu_reg[next_reg++] = qpu_rb(i);
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assert(next_reg == ARRAY_SIZE(allocate_to_qpu_reg));
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foreach(node, &c->instructions) {
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struct qinst *qinst = (struct qinst *)node;
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if (qinst->dst.file == QFILE_TEMP)
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reg_uses_remaining[qinst->dst.index]++;
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for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
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if (qinst->src[i].file == QFILE_TEMP)
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reg_uses_remaining[qinst->src[i].index]++;
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}
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if (qinst->op == QOP_FRAG_Z)
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reg_in_use[3 + 32 + QPU_R_FRAG_PAYLOAD_ZW] = true;
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}
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foreach(node, &c->instructions) {
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struct qinst *qinst = (struct qinst *)node;
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for (int i = 0; i < qir_get_op_nsrc(qinst->op); i++) {
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int index = qinst->src[i].index;
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if (qinst->src[i].file != QFILE_TEMP)
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continue;
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if (reg_allocated[index] == -1) {
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fprintf(stderr, "undefined reg use: ");
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qir_dump_inst(qinst);
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fprintf(stderr, "\n");
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} else {
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reg_uses_remaining[index]--;
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if (reg_uses_remaining[index] == 0)
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reg_in_use[reg_allocated[index]] = false;
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}
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}
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if (qinst->dst.file == QFILE_TEMP) {
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if (reg_allocated[qinst->dst.index] == -1) {
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int alloc;
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for (alloc = 0;
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alloc < ARRAY_SIZE(reg_in_use);
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alloc++) {
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struct qpu_reg reg = allocate_to_qpu_reg[alloc];
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switch (qinst->op) {
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case QOP_PACK_SCALED:
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/* The pack flags require an
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* A-file register.
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*/
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if (reg.mux != QPU_MUX_A)
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continue;
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break;
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case QOP_TEX_RESULT:
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case QOP_TLB_COLOR_READ:
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/* Only R4-generating
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* instructions get to store
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* values in R4 for now, until
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* we figure out how to do
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* interference.
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*/
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if (reg.mux != QPU_MUX_R4)
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continue;
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break;
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case QOP_FRAG_Z:
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if (reg.mux != QPU_MUX_B ||
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reg.addr != QPU_R_FRAG_PAYLOAD_ZW) {
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continue;
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}
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break;
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default:
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if (reg.mux == QPU_MUX_R4)
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continue;
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break;
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}
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if (!reg_in_use[alloc])
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break;
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}
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assert(alloc != ARRAY_SIZE(reg_in_use) && "need better reg alloc");
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reg_in_use[alloc] = true;
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reg_allocated[qinst->dst.index] = alloc;
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temp_registers[qinst->dst.index] = allocate_to_qpu_reg[alloc];
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}
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reg_uses_remaining[qinst->dst.index]--;
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if (reg_uses_remaining[qinst->dst.index] == 0) {
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reg_in_use[reg_allocated[qinst->dst.index]] =
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false;
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}
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}
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}
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return temp_registers;
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}
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