A subpass in gfxbench has the depth buffer present, but not written to,
for a render pass using the depth buffer as an input attachment. We can
skip single-prim-mode and the associated "oh no don't use sysmem" in that
case.
Improves gfxbench vk-5-normal perf by 1.56193% +/- 0.0743035% (n=14).
Part of #6327.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18241>
Not knowing whether we deal with the NV or EXT extension
makes implementation difficult for Intel HW.
NV support will be dropped at some point, so
this ugliness will go away eventually.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
A task shader must use this instruction to specify the dimensions
of the launched mesh shader workgroups.
It is a terminating instruction.
When the task shader doesn't have the optional payload, use the
pre-existing launch_mesh_workgroups intrinsics.
When the task shader has a payload, use a new
launch_mesh_workgroups_with_payload_deref intrinsics which has
a deref that refers to the payload variable.
We also add this new intrinsic to nir_lower_io which lowers this
to the pre-existing explicit intrinsic.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Just use the task_payload NIR storage class for this.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
This is a per-primitive builtin output which indicates that a
primitive should be culled (deleted) from the output.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Use the set_vertex_and_primitive_count intrinsic to
express the number of vertices and primitives that the
mesh shader workgroup outputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
Indicates support for the EXT_mesh_shader SPIR-V capabilities.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
They are not defined as per-primitive in the EXT, but they behave
like per-primitive outputs so it's easier to treat them like that.
They may still require special treatment in the backend in order to
control where and how they are stored.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18366>
This is a common pattern. Make it more ergonomic. With the help of Coccinelle:
@@
expression E;
expression R;
expression instruction;
@@
-instruction->src[E] = bi_replace_index(instruction->src[E], R);
+bi_replace_src(instruction, E, R);
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Prior to register allocation, destinations must be in SSA form, except for the
"fake SSA" briefly used in the current RA (for which bi_is_ssa returns true
anyway). These asserts duplicate the asserts in the validator. If there's any
coverage lost here, that's just a sign the validator needs to run more often.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Frequently, we want to iterate over the SSA variables read by an instruction,
while skipping over constants and uniforms. Add and use a macro for this
pattern. A few redundant asserts are removed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Now that variables have flat naming (no more SSA/reg distinction), we can just
use .value directly. This cleans up the RA a bit.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Now that non-SSA nodes are an internal implementation detail of RA, the
entrypoints should be made private to make sure no other passes use the
RA-specific liveness analysis.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
We've already broken SSA irreparably at this point. We can just change what
"normal" means and avoid the disjointed indexing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
nir_invalidate_divergence was introduced in aa765c54bd ("pan/bi: Add divergent
intrinsic lowering pass"), which needed divergence information for a late NIR
pass but not otherwise in the backend. Unfortunately, nir_convert_from_ssa is
less aggressive about coalescing when divergence information makes it look like
the coalescing would make the code worse -- even though that's not actually an
issue on Mali.
Now that we don't use nir_convert_from_ssa, we don't need the hack.
Likewise for the vec.reg hack, which was introduced because the split/collect
cache relies on SSA form.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Don't call nir_convert_from_ssa, preserve the SSA from NIR. This gets us real
SSA for all frontend passes. The RA becomes a black box that takes SSA in and
outputs register allocated code out. The "broken" SSA form never escapes RA,
which means we can clean up special cases in the rest of the compiler. It also
gets us ready for exploiting SSA form in the RA itself.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Adapted from NIR's liveness analysis. This is different from our non-SSA
liveness pass for a few reasons:
1. It must handle phi nodes. This implies significant changes to the worklist
algorithm.
2. It only handles SSA. It doesn't need funny labelling schemes for
handling nir_registers in parallel with SSA defs.
3. It is scalar-only. The vector liveness information isn't interesting when
vectors are handled via COLLECT and SPLIT. This means it uses a bitset (uses
8x less memory to store livenss information, should be easier on the caches
too).
Eventually, this will become our only pre-RA liveness pass. For now, both passes
are maintained in parallel: the SSA pass used before out-of-SSA, the non-SSA
pass used after out-of-SSA and before RA, and the post-RA pass used after RA.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Pre-RA scheduling can move instructions around in nontrivial ways, yet it must
maintain the IR's ordering invariants (for preloads, phis, etc.) Running
validation before and after makes scheduler bugs more obvious.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
We can get BRANCHZ.i16 since we lower JUMP early. This seems to have worked
before mainly by chance. With the change to how we optimize, we can get code
sequences like:
block2 {
BRANCHZ.i16.eq u256, u256 -> block5
BRANCHZ.i16.eq u256, u256 -> block4
} -> block5 from block1
which would choke the assert.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
