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anv: replace VK_SHADER_STAGE_[TASK|MESH]_BIT_NV with VK_SHADER_STAGE_[TASK|MESH]_BIT_EXT
They have the same numerical values, so nothing changes. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371>
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commit
b3354afd89
4 changed files with 15 additions and 15 deletions
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@ -483,8 +483,8 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
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stages &= VK_SHADER_STAGE_ALL_GRAPHICS |
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((cmd_buffer->device->vk.enabled_extensions.NV_mesh_shader ||
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cmd_buffer->device->vk.enabled_extensions.EXT_mesh_shader) ?
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(VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV) : 0);
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(VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT) : 0);
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pipe_state = &cmd_buffer->state.gfx.base;
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break;
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@ -520,8 +520,8 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
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* This means that we have to upload the descriptor set
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* as an 64-bit address in the push constants.
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*/
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bool update_desc_sets = stages & (VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV |
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bool update_desc_sets = stages & (VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT |
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VK_SHADER_STAGE_RAYGEN_BIT_KHR |
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VK_SHADER_STAGE_ANY_HIT_BIT_KHR |
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VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR |
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@ -805,8 +805,8 @@ void anv_CmdPushConstants(
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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if (stageFlags & (VK_SHADER_STAGE_ALL_GRAPHICS |
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VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV)) {
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VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT)) {
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struct anv_cmd_pipeline_state *pipe_state =
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&cmd_buffer->state.gfx.base;
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@ -1894,8 +1894,8 @@ anv_get_physical_device_properties_1_1(struct anv_physical_device *pdevice,
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}
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if (pdevice->vk.supported_extensions.NV_mesh_shader ||
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pdevice->vk.supported_extensions.EXT_mesh_shader) {
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scalar_stages |= VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV;
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scalar_stages |= VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT;
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}
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p->subgroupSupportedStages = scalar_stages;
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p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
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@ -2042,8 +2042,8 @@ anv_get_physical_device_properties_1_3(struct anv_physical_device *pdevice,
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p->maxSubgroupSize = 32;
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p->maxComputeWorkgroupSubgroups = pdevice->info.max_cs_workgroup_threads;
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p->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT |
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VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV;
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VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT;
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p->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
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p->maxPerStageDescriptorInlineUniformBlocks =
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@ -1353,7 +1353,7 @@ anv_graphics_pipeline_init_keys(struct anv_graphics_pipeline *pipeline,
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}
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assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT ||
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pipeline->active_stages & VK_SHADER_STAGE_MESH_BIT_NV);
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pipeline->active_stages & VK_SHADER_STAGE_MESH_BIT_EXT);
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}
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static bool
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@ -3050,7 +3050,7 @@ cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer,
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struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx;
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const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline;
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if (dirty_stages & VK_SHADER_STAGE_TASK_BIT_NV &&
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if (dirty_stages & VK_SHADER_STAGE_TASK_BIT_EXT &&
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anv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) {
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const struct anv_shader_bin *shader = pipeline->shaders[MESA_SHADER_TASK];
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@ -3073,7 +3073,7 @@ cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer,
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}
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}
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if (dirty_stages & VK_SHADER_STAGE_MESH_BIT_NV &&
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if (dirty_stages & VK_SHADER_STAGE_MESH_BIT_EXT &&
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anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) {
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const struct anv_shader_bin *shader = pipeline->shaders[MESA_SHADER_MESH];
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@ -3570,8 +3570,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
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dirty & VK_SHADER_STAGE_ALL_GRAPHICS);
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#if GFX_VERx10 >= 125
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cmd_buffer_flush_mesh_inline_data(
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cmd_buffer, dirty & (VK_SHADER_STAGE_TASK_BIT_NV |
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VK_SHADER_STAGE_MESH_BIT_NV));
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cmd_buffer, dirty & (VK_SHADER_STAGE_TASK_BIT_EXT |
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VK_SHADER_STAGE_MESH_BIT_EXT));
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#endif
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}
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