Our get_buffer/image_memory_requirements() pad TRANSFER_SRC resources
with V3D_TFU_READAHEAD_SIZE, so allocating the reported requirements of
a resource of exactly maxMemoryAllocationSize failed with
VK_ERROR_OUT_OF_DEVICE_MEMORY.
Accept up to one extra page over the limit: since the allocation size
is page-aligned, that covers any sub-page padding.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42179>
This prevents holding open file descriptors after physical devices
are enumerated. This also prevents potential (and unknown) multithreading
issues with the winsys being shared between more than one logical device.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41824>
The winsys will be moved to logical devices. This creates a
ac_drm_device on-demand to make the call faster because otherwise it's
too slow for a function that can be called every frame.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41824>
Also adds dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.7.10
to CI skips due to it having a runtime of > 5m with the following:
Test case 'dEQP-VK.reconvergence.subgroup_uniform_control_flow_ballot.compute.nesting4.7.10'..
NotSupported (No compatible memory type found at vkMemUtil.cpp:652)
which hits the timeout.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41833>
- Split pseudo-instruction legalization into pre/post RA stages.
- Add vote pseudo-op and lowering.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41833>
Replaces the no-op subgroup implementation with a real one, covering
what's needed for VK_SUBGROUP_FEATURE_BASIC_BIT.
The setl instruction will only execute on the first valid instance within
a slot/thread-group (comprising 32 instances/threads, i.e. our subgroup size),
which enables a subgroupElect() implementation.
Instances within a slot execute in lockstep which allows us to continue
discarding subgroup barriers as per the no-op implementation.
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41833>
There are 12 TI AM62 Starter Kit boards available in the farm for this testing.
Signed-off-by: Robert Mazur <robert.mazur@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42172>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 49fb361c0a ("aco: don't emit workgroup-scope p_barrier for single-wave workgroups")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42214>
Enable getting and using the optimal number of temps instead of the maximum.
Instead of going straight to the maximum amount and then spilling,
register allocation will now first try to allocate with the optimal
amount of temps, then try with the maximum, then spill.
Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42078>
Too many boolean variables handling what is essentially the same state
of the register allocation cause unnecessary complexity. Moved to an
enum and a single struct member in the ra_ctx.
Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42078>
Adds force spilling control and optimal allocation disabling debug variables.
Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42078>
To avoid extra unnecessary calls of the function when temp spilling
happens multiple times within a shader func
Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42078>
Instructions that use a vec as a source were not having their subsequent
vtxin registers taken into account for reuse, just the 1st register in
the vec. Due to how vtxin regs function, reusing them while they are
still live can cause undefined behaviour. This change sets the registers
for all vtxin regs in the vec.
Fixes: 0ea39c63 ("pco: Use vertex input registers in register allocation")
Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42078>
[WHY]
Refactoring reset pipe function to prevent future command buffer bloat.
[HOW]
Split the reset pipes function into RMCM detachment and backend register
reset. Created a pipe setup function that calls MPC reset followed by 3dlut fastload and
backend register reset to the end of program frontend.
Acked-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Farhan Rouf <Farhan.Rouf@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42033>
[WHY]
Want to support Display DCC for input + Centralized DCC for output
[HOW]
Updated DCC API to only include needed params, and updated plane writer
to support DCC.
Acked-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Brendan Steve Leder <BrendanSteve.Leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42033>
[WHY]
FP16 with non-linear gamma is not a regular format. But to support
multi-pass with FP16 intermediate format, the support needs to be added.
Acked-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Navid Assadian <Navid.Assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42033>
[WHY]
Color corruption observed when playing a rotated HDR AV1 Video on an SDR
monitor. The cause of the corruption was erroneously repeated 3dlut
fastload configs throught a single vpe descriptor.
[HOW]
- The handling of the state of the config writer call back in
conjunction with missing the completion of the fastload config
resulted in the fastload being cached in both the frame programmming
and stream op config when it should be cached in neither.
The sequence was set stream/op sharing = 0, create 3dlut fastload
config, set stream/op config cache to 1, change the config type which
triggers a config completion and caches the config due to the
stream/op confi cache being set to 1.
Acked-by: Peyton Lee <peytolee@amd.com>
Signed-off-by: Jesse Agate <Jesse.Agate@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42033>
