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ac,radeonsi,radv: add has_desc_resource_level var instead of gfx_level check

Browse source 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41969>
This commit is contained in:
Yogesh Mohan Marimuthu 2026-06-05 14:00:14 +05:30 • committed by Marge Bot
parent 6ff16a87ae
commit 418c4cfa67
17 changed files with 54 additions and 16 deletions
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12
src/amd/common/ac_descriptors.c
View file

@ -520,7 +520,7 @@ ac_build_gfx10_texture_descriptor(const struct radeon_info *info, const struct a
S_00A004_WIDTH_LO(state->width - 1);
desc[2] = S_00A008_WIDTH_HI((state->width - 1) >> 2) |
S_00A008_HEIGHT(state->height - 1) |
S_00A008_RESOURCE_LEVEL(info->gfx_level < GFX11);
S_00A008_RESOURCE_LEVEL(info->compiler_info.has_desc_resource_level);
desc[3] = S_00A00C_DST_SEL_X(ac_map_swizzle(state->swizzle[0])) |
S_00A00C_DST_SEL_Y(ac_map_swizzle(state->swizzle[1])) |
S_00A00C_DST_SEL_Z(ac_map_swizzle(state->swizzle[2])) |
@ -844,7 +844,7 @@ ac_set_buf_desc_word3(const enum amd_gfx_level gfx_level, const struct ac_buffer
*rsrc_word3 |= (gfx_level >= GFX12 ? S_008F0C_FORMAT_GFX12(fmt->img_format) :
S_008F0C_FORMAT_GFX10(fmt->img_format)) |
S_008F0C_OOB_SELECT(state->gfx10_oob_select) |
S_008F0C_RESOURCE_LEVEL(gfx_level < GFX11);
S_008F0C_RESOURCE_LEVEL(state->has_desc_resource_level);
if (gfx_level >= GFX12) {
*rsrc_word3 |= S_008F0C_COMPRESSION_EN(state->gfx12.compression_en) |
@ -886,7 +886,8 @@ ac_build_buffer_descriptor(const enum amd_gfx_level gfx_level, const struct ac_b
}
void
ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level, uint64_t va, uint32_t size, uint32_t desc[4])
ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level, bool has_desc_resource_level,
uint64_t va, uint32_t size, uint32_t desc[4])
{
const struct ac_buffer_state ac_state = {
.va = va,
@ -896,13 +897,15 @@ ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level, uint64_t va,
PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W,
},
.gfx10_oob_select = V_008F0C_OOB_SELECT_RAW,
.has_desc_resource_level = has_desc_resource_level,
};
ac_build_buffer_descriptor(gfx_level, &ac_state, desc);
}
void
ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level, uint64_t va, uint32_t size, uint32_t stride, uint32_t desc[4])
ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level, bool has_desc_resource_level,
uint64_t va, uint32_t size, uint32_t stride, uint32_t desc[4])
{
assert(gfx_level >= GFX11);
@ -915,6 +918,7 @@ ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level, uint64_t va, u
},
.stride = stride,
.gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
.has_desc_resource_level = has_desc_resource_level,
.swizzle_enable = 3, /* 16B */
.index_stride = 2, /* 32 elements */
};

3
src/amd/common/ac_descriptors.h
View file

@ -327,6 +327,7 @@ struct ac_buffer_state {
uint32_t index_stride : 2;
uint32_t add_tid : 1;
uint32_t gfx10_oob_select : 2;
uint32_t has_desc_resource_level : 1;
struct {
uint32_t compression_en : 1;
@ -346,12 +347,14 @@ ac_build_buffer_descriptor(const enum amd_gfx_level gfx_level,
void
ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level,
bool has_desc_resource_level,
uint64_t va,
uint32_t size,
uint32_t desc[4]);
void
ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level,
bool has_desc_resource_level,
uint64_t va,
uint32_t size,
uint32_t stride,

2
src/amd/common/ac_gpu_info.c
View file

@ -426,6 +426,8 @@ ac_fill_compiler_info(struct radeon_info *info, const struct drm_amdgpu_info_dev
out->has_ngg_passthru_no_msg = false;
out->has_vrs_frag_pos_z_bug = true;
}
out->has_desc_resource_level = info->gfx_level < GFX11;
}
void

3
src/amd/common/ac_gpu_info.h
View file

@ -203,8 +203,9 @@ struct ac_compiler_info {
uint32_t has_cs_regalloc_hang_bug : 1;
/* GFX6-GFX12, except GFX9: SMEM loads on NULL PRT page don't work. */
uint32_t has_smem_with_null_prt_bug : 1;
uint32_t has_desc_resource_level : 1;
uint32_t reserved : 3;
uint32_t reserved : 2;
};
struct radeon_info {

3
src/amd/compiler/aco_ir.cpp
View file

@ -121,6 +121,8 @@ init_program(Program* program, Stage stage, const struct aco_shader_info* info,
program->dev.fused_mad_mix = options->compiler_info->has_fma_mix;
program->dev.has_mad32 = options->compiler_info->has_mad32;
program->dev.has_desc_resource_level = options->compiler_info->has_desc_resource_level;
if (program->gfx_level >= GFX12) {
program->dev.scratch_global_offset_min = -8388608;
program->dev.scratch_global_offset_max = 8388607;
@ -1953,6 +1955,7 @@ load_scratch_resource(Program* program, Builder& bld, unsigned resume_idx,
ac_state.index_stride = program->wave_size == 64 ? 3u : 2u;
ac_state.add_tid = true;
ac_state.gfx10_oob_select = V_008F0C_OOB_SELECT_RAW;
ac_state.has_desc_resource_level = program->dev.has_desc_resource_level;
ac_build_buffer_descriptor(program->gfx_level, &ac_state, desc);

1
src/amd/compiler/aco_ir.h
View file

@ -2304,6 +2304,7 @@ struct DeviceInfo {
bool sram_ecc_enabled = false;
bool has_point_sample_accel = false;
bool has_gfx6_mrt_export_bug = false;
bool has_desc_resource_level = false;
int32_t scratch_global_offset_min;
int32_t scratch_global_offset_max;

6
src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp
View file

@ -817,7 +817,8 @@ Temp
get_mubuf_global_rsrc(Builder& bld, Temp addr)
{
uint32_t desc[4];
ac_build_raw_buffer_descriptor(bld.program->gfx_level, 0, 0xffffffff, desc);
ac_build_raw_buffer_descriptor(bld.program->gfx_level, bld.program->dev.has_desc_resource_level,
0, 0xffffffff, desc);
if (addr.type() == RegType::vgpr)
return bld.pseudo(aco_opcode::p_create_vector, bld.def(s4), Operand::zero(), Operand::zero(),
@ -1592,7 +1593,8 @@ visit_load_constant(isel_context* ctx, nir_intrinsic_instr* instr)
Builder bld(ctx->program, ctx->block);
uint32_t desc[4];
ac_build_raw_buffer_descriptor(ctx->options->gfx_level, 0, 0, desc);
ac_build_raw_buffer_descriptor(ctx->options->gfx_level,
ctx->program->dev.has_desc_resource_level, 0, 0, desc);
unsigned base = nir_intrinsic_base(instr);
unsigned range = nir_intrinsic_range(instr);

5
src/amd/vulkan/nir/radv_nir_lower_descriptors.c
View file

@ -23,6 +23,7 @@ typedef struct {
bool disable_aniso_single_level;
bool has_image_load_dcc_bug;
bool disable_tg4_trunc_coord;
bool has_desc_resource_level;
const struct radv_shader_args *args;
const struct radv_shader_info *info;
@ -189,7 +190,8 @@ load_inline_buffer_descriptor(nir_builder *b, lower_descriptors_state *state, ni
{
uint32_t desc[4];
ac_build_raw_buffer_descriptor(state->gfx_level, (uint64_t)state->address32_hi << 32, 0xffffffff, desc);
ac_build_raw_buffer_descriptor(state->gfx_level, state->has_desc_resource_level, (uint64_t)state->address32_hi << 32,
0xffffffff, desc);
return nir_vec4(b, rsrc, nir_imm_int(b, desc[1]), nir_imm_int(b, desc[2]), nir_imm_int(b, desc[3]));
}
@ -688,6 +690,7 @@ radv_nir_lower_descriptors(nir_shader *shader, const struct radv_compiler_info *
compiler_info->key.disable_aniso_single_level && compiler_info->ac->gfx_level < GFX8,
.has_image_load_dcc_bug = compiler_info->ac->has_image_load_dcc_bug,
.disable_tg4_trunc_coord = !compiler_info->ac->conformant_trunc_coord && !compiler_info->key.disable_trunc_coord,
.has_desc_resource_level = compiler_info->ac->has_desc_resource_level,
.args = &stage->args,
.info = &stage->info,
.layout = &stage->layout,

1
src/amd/vulkan/radv_buffer_view.c
View file

@ -49,6 +49,7 @@ radv_make_texel_buffer_descriptor(struct radv_device *device, uint64_t va, VkFor
},
.stride = stride,
.gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
.has_desc_resource_level = pdev->info.compiler_info.has_desc_resource_level,
};
ac_build_buffer_descriptor(pdev->info.gfx_level, &ac_state, state);

9
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -6898,7 +6898,8 @@ radv_write_vertex_descriptor(const struct radv_cmd_buffer *cmd_buffer, const str
* - 3: offset >= NUM_RECORDS (Raw)
*/
int oob_select = stride ? V_008F0C_OOB_SELECT_STRUCTURED : V_008F0C_OOB_SELECT_RAW;
rsrc_word3 |= S_008F0C_OOB_SELECT(oob_select) | S_008F0C_RESOURCE_LEVEL(chip < GFX11);
rsrc_word3 |=
S_008F0C_OOB_SELECT(oob_select) | S_008F0C_RESOURCE_LEVEL(pdev->info.compiler_info.has_desc_resource_level);
}
uint64_t va = vbo_info.va;
@ -7057,7 +7058,8 @@ radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
}
}
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, va, size, desc);
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, pdev->info.compiler_info.has_desc_resource_level, va, size,
desc);
}
desc_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
@ -8337,7 +8339,8 @@ radv_bind_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, const VkBindDescri
uint64_t va = range->va + pBindDescriptorSetsInfo->pDynamicOffsets[dyn_idx];
const uint32_t size = no_dynamic_bounds ? 0xffffffffu : range->size;
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, va, size, dst);
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, pdev->info.compiler_info.has_desc_resource_level, va,
size, dst);
}
descriptors_state->dynamic_descriptors_offsets[set_idx] = dynamic_offset_start;

3
src/amd/vulkan/radv_descriptors.h
View file

@ -65,7 +65,8 @@ radv_write_buffer_descriptor(struct radv_device *device, VkDescriptorType descri
* we return from vkGetBufferMemoryRequirements) and this allows the shader compiler to create
* more efficient 8/16-bit buffer accesses.
*/
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, va, align(range, 4), dst);
ac_build_raw_buffer_descriptor(pdev->info.gfx_level, pdev->info.compiler_info.has_desc_resource_level, va,
align(range, 4), dst);
}
static ALWAYS_INLINE void

6
src/amd/vulkan/radv_queue.c
View file

@ -245,6 +245,7 @@ radv_set_ring_buffer(const struct radv_physical_device *pdev, struct radeon_wins
.index_stride = index_stride,
.add_tid = add_tid,
.gfx10_oob_select = oob_select,
.has_desc_resource_level = pdev->info.compiler_info.has_desc_resource_level,
};
ac_build_buffer_descriptor(pdev->info.gfx_level, &ac_state, desc);
@ -332,8 +333,9 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon
if (ge_rings_bo) {
assert(pdev->info.gfx_level >= GFX11);
ac_build_attr_ring_descriptor(pdev->info.gfx_level, radv_buffer_get_va(ge_rings_bo),
pdev->info.total_attribute_pos_prim_ring_size, 0, &desc[0]);
ac_build_attr_ring_descriptor(pdev->info.gfx_level, pdev->info.compiler_info.has_desc_resource_level,
radv_buffer_get_va(ge_rings_bo), pdev->info.total_attribute_pos_prim_ring_size, 0,
&desc[0]);
}
desc += 4;

1
src/amd/vulkan/tools/radv_debug_hang.c
View file

@ -1172,6 +1172,7 @@ radv_trap_handler_init(struct radv_device *device)
},
.gfx10_oob_select = V_008F0C_OOB_SELECT_RAW,
.stride = 4, /* Used for VGPRs dump. */
.has_desc_resource_level = pdev->info.compiler_info.has_desc_resource_level,
};
ac_build_buffer_descriptor(pdev->info.gfx_level, &ac_state, desc);

9
src/gallium/drivers/radeonsi/gfx/si_nir_lower_abi.c
View file

@ -60,6 +60,7 @@ static nir_def *build_attr_ring_desc(nir_builder *b, struct si_shader *shader,
uint32_t desc[4];
ac_build_attr_ring_descriptor(sel->screen->info.gfx_level,
sel->screen->info.compiler_info.has_desc_resource_level,
(uint64_t)sel->screen->info.address32_hi << 32,
0xffffffff, stride, desc);
@ -80,8 +81,9 @@ static nir_def *build_tess_ring_desc(nir_builder *b, struct si_screen *screen,
uint32_t desc[4];
ac_build_raw_buffer_descriptor(screen->info.gfx_level,
(uint64_t)screen->info.address32_hi << 32,
0xffffffff, desc);
screen->info.compiler_info.has_desc_resource_level,
(uint64_t)screen->info.address32_hi << 32,
0xffffffff, desc);
nir_def *comp[4] = {
addr,
@ -162,6 +164,7 @@ static bool build_gsvs_ring_desc(nir_builder *b, struct lower_abi_state *s)
.index_stride = 1,
.add_tid = true,
.gfx10_oob_select = V_008F0C_OOB_SELECT_DISABLED,
.has_desc_resource_level = sel->screen->info.compiler_info.has_desc_resource_level,
};
uint32_t tmp_desc[4];
@ -198,6 +201,7 @@ static nir_def *build_task_ring_desc(nir_builder *b, struct lower_abi_state *s,
.format = PIPE_FORMAT_R32_FLOAT,
.swizzle = { PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W },
.gfx10_oob_select = V_008F0C_OOB_SELECT_DISABLED,
.has_desc_resource_level = screen->info.compiler_info.has_desc_resource_level,
};
unsigned desc[4];
@ -227,6 +231,7 @@ static nir_def *build_mesh_scratch_ring_desc(nir_builder *b, struct lower_abi_st
.format = PIPE_FORMAT_R32_FLOAT,
.swizzle = { PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W },
.gfx10_oob_select = V_008F0C_OOB_SELECT_DISABLED,
.has_desc_resource_level = screen->info.compiler_info.has_desc_resource_level,
};
unsigned desc[4];

1
src/gallium/drivers/radeonsi/gfx/si_nir_lower_resource.c
View file

@ -39,6 +39,7 @@ static nir_def *load_ubo_desc_fast_path(nir_builder *b, nir_def *addr_lo,
PIPE_SWIZZLE_W,
},
.gfx10_oob_select = V_008F0C_OOB_SELECT_RAW,
.has_desc_resource_level = sel->screen->info.compiler_info.has_desc_resource_level,
};
uint32_t desc[4];

2
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -994,6 +994,7 @@ static void si_init_buffer_resources(struct si_context *sctx,
PIPE_SWIZZLE_W,
},
.gfx10_oob_select = V_008F0C_OOB_SELECT_RAW,
.has_desc_resource_level = sctx->screen->info.compiler_info.has_desc_resource_level,
};
/* Initialize buffer descriptors, so that we don't have to do it at bind time. */
@ -1441,6 +1442,7 @@ void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource
.stride = stride,
.swizzle_enable = swizzle_enable,
.gfx10_oob_select = V_008F0C_OOB_SELECT_DISABLED,
.has_desc_resource_level = sctx->screen->info.compiler_info.has_desc_resource_level,
.index_stride = index_stride,
.element_size = element_size,
.add_tid = add_tid,

3
src/gallium/drivers/radeonsi/si_state.c
View file

@ -3541,6 +3541,7 @@ void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf
},
.stride = stride,
.gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
.has_desc_resource_level = screen->info.compiler_info.has_desc_resource_level,
};
ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[0]);
@ -3623,6 +3624,7 @@ static void cdna_emu_make_image_descriptor(struct si_screen *screen, struct si_t
},
.stride = stride,
.gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
.has_desc_resource_level = screen->info.compiler_info.has_desc_resource_level,
};
ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[0]);
@ -4467,6 +4469,7 @@ static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
*/
.gfx10_oob_select = v->elem[i].stride ? V_008F0C_OOB_SELECT_STRUCTURED
: V_008F0C_OOB_SELECT_RAW,
.has_desc_resource_level = sscreen->info.compiler_info.has_desc_resource_level,
};
ac_set_buf_desc_word3(sscreen->info.gfx_level, &buffer_state, &v->elem[i].rsrc_word3);