Commit graph

165886 commits

Author SHA1 Message Date
Leandro Ribeiro
cd2854ccfb loader: rename loader_open_render_node() to loader_open_render_node_platform_device()
This function ignore devices that are not on the platform bus. So rename
it to better reflect that.

Signed-off-by: Leandro Ribeiro <leandro.ribeiro@collabora.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24825>
2023-10-17 20:31:13 +00:00
Yiwei Zhang
3fdea1567d venus: properly expose KHR_external_fence/sempahore_fd
Summary:
1. hide those extensions for vtest since there's no export support
2. do block waiting upon export without implicit fencing support

Fixes: 68a478870d ("venus: expose KHR_external_fence/sempahore_fd extensions")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25633>
2023-10-17 20:12:07 +00:00
Faith Ekstrand
4591c525ea nvk: Implement VK_EXT_depth_bias_control
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9628
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25765>
2023-10-17 18:35:03 +00:00
Faith Ekstrand
8639c311bd nvk: Re-sort device features
Vulkan versions, then KHR, then EXT, then vendor.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25765>
2023-10-17 18:35:03 +00:00
Faith Ekstrand
c6509ffcea nvk: Add a nvk_cmd_buffer_dirty_render_pass() helper
This makes the dirtying work properly in the case where dynamic
rendering is being used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25765>
2023-10-17 18:35:03 +00:00
Felix DeGrood
b561bcd78c anv: set ComputeMode.PixelAsyncComputeThreadLimit = 4
Heuristic-based optimization throttling CCS work (async compute).
Without throttling, background compute work consumes all threads,
deminishing performance gains by running dispatch in parallel with
3D work.

Optimization is heuristics based, meaning a workload might slow
down when using async compute.

Best value: PixelAsyncComputeThreadLimit = 4. On DG2, this
equates to a max CCS thread occupancy of 37.5%.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25508>
2023-10-17 18:09:29 +00:00
Marek Olšák
8ff4847b64 nir/algebraic: use only signed_zero_preserve_* for addition by 0 patterns, etc.
Some GLSL versions will set inf_preserve but not the other flags.
Additions by 0 only affect signed zeros.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25392>
2023-10-17 17:27:12 +00:00
Marek Olšák
f3886e9c02 nir: split FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP* flags
GLSL doesn't preserve NaNs, but it optionally preserves Infs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25392>
2023-10-17 17:27:12 +00:00
Rohan Garg
b94b784492 anv: fix debug string for PC flush
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Fixes: fc5cb54 ('anv: Add debug messages for DEBUG_PIPE_CONTROL')
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25690>
2023-10-17 14:31:16 +00:00
Lucas Stach
336799481d etnaviv: zero shared TS metadata block
Make sure to zero the shared TS metadata memory. Without this invalid
TS data may be mistaken as being valid, causing GPU hangs.

CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25751>
2023-10-17 13:34:19 +00:00
Lucas Stach
b4c24d5978 etnaviv: use correct blit box sizes when copying resource
The padded width/height is stored in samples, while the blit box
dimensions need to be specified in pixels. Use the unpadded
width/height of the resource levels to generate the blit box
dimensions used to copy a resource. The blit code already extends
those sizes to the padded sizes when necessary and possible.
Fixes crashes in some piglit tests with MSAA active.

CC: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25751>
2023-10-17 13:34:19 +00:00
Vinson Lee
5612f9a704 broadcom/qpu: Remove duplicate variable opcode
Fix defect reported by Coverity Scan.

Evaluation order violation (EVALUATION_ORDER)
write_write_typo: In opcode = opcode = desc->opcode_first, opcode is
written twice with the same value.

Fixes: 3b20208f03 ("broadcom/qpu: add pack/unpack support for v71")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25735>
2023-10-17 12:31:33 +00:00
Lionel Landwerlin
b207608995 intel/ds: provide names for different events of a timeline's row
Previously all items on a timeline row would have the same name. This
change uses the tracepoint names to put into the timeline instead.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25730>
2023-10-17 11:19:13 +00:00
Lionel Landwerlin
6499c43cc7 u_trace: generate tracepoint name array in perfetto header
The driver glue doesn't have access to that information in a
centralized place. If you want to generate perfetto iid, you need
access to all names.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25730>
2023-10-17 11:19:13 +00:00
Lionel Landwerlin
1afc876afd u_trace: generate tracepoint index parameter in perfetto callbacks
Useful to figure out what's the tracepoint name you're implementing.
We'll use this in the intel perfetto integration glue to index into an
array of perfetto iid.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25730>
2023-10-17 11:19:13 +00:00
Hyunjun Ko
960441d5a3 anv: don't flush_llc on gen9
Fixes: 3d993e63bb ("anv: Enable barrier handling on video engines ")
Closes: mesa/mesa#9988

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25762>
2023-10-17 12:28:06 +02:00
Gert Wollny
e891c78af1 virgl: Fix logic for reporting PIPE_MIRROR_CLAMP
Fixes: 9efe50c83 (virgl: report MIRROR_CLAMP features better)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25755>
2023-10-17 08:55:29 +00:00
Dave Airlie
d6613deed9 intel-clc: avoid using spirv-linker.
There is not real need to use the spirv-linker here at all,
we can just read all the CL C files into one buffer, then compile
that buffer in a single pass.

This worksaround an issue seen with llvm17 and opaque pointers
and the spirv linker.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25759>
2023-10-17 13:53:52 +10:00
Marek Olšák
843f2eb3c8 radeonsi/ci: update gfx1100 results
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25484>
2023-10-17 00:31:07 +00:00
Marek Olšák
8211635c44 winsys/amdgpu: don't send CP_GFX_SHADOW chunk if shadow address is not set
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25484>
2023-10-17 00:31:07 +00:00
Marek Olšák
6224630e43 radeonsi: disable register shadowing without SR-IOV to fix bad performance
Fixes: f71607c8d3 - radeonsi/gfx11: enable register shadowing by default

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25484>
2023-10-17 00:31:07 +00:00
Marek Olšák
865cab6a1c ac/gpu_info: don't allow register shadowing with SR-IOV due to bad performance
This is only for gfx11.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25484>
2023-10-17 00:31:07 +00:00
Iván Briano
abf5eb5753 anv: advertise VK_KHR_global_priority_queue
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25758>
2023-10-16 23:39:58 +00:00
Friedrich Vock
f8eec4c4e3 radv/rt: Reject hits within 10ULP of previous hits in emulated RT
This is an alternative workaround that fixes double hits on shared edges
failing some watertightness CTS tests.

Fixes: e034ba1c44 ("radv/rt: Miss rays that hit the triangle's v edge")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24093>
2023-10-16 23:10:20 +00:00
Lionel Landwerlin
f900b763b1 anv: workaround Gfx11 with optimized state emission
No real explanation so far.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 50f6903bd9 ("anv: add new low level emission & dirty state tracking")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9781
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25750>
2023-10-16 19:48:28 +00:00
Marek Olšák
d8a41a27b9 winsys/amdgpu: pad gfx and compute IBs with only 1 NOP
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
87e9fafaa8 winsys/amdgpu: correctly pad noop IBs for RADEON_NOOP=1
We need to use ib_pad_dw_mask, not ib_alignment.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
e6d4552b67 winsys/amdgpu: properly pad the IB in amdgpu_submit_gfx_nop
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
5a5629f766 ac/gpu_info: set gfx and compute IB padding to only 8 dwords
This is what the kernel reports and what PAL seems to be doing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
395b7ce364 ac/gpu_info: conservatively decrease IB alignment and padding to 256B
This should be large enough for all engines.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
42aedd627e ac/gpu_info: drop the hack unifying all IB alignments
We overalign it anyway, so there is no change in behavior.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
5edc0da8ec ac/gpu_info: move ib_pad_dw_mask into ip[]
No change in behavior.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:34 +00:00
Marek Olšák
e0813c5477 ac/gpu_info: split ib_alignment as ip[type].ib_alignment
No change in behavior. The previous overalignment is preserved.

It sets ib_pad_dw_mask sooner.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
2023-10-16 16:16:33 +00:00
Thong Thai
cba898a530 frontends/va/config: report max width and height for encoding/decoding
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25716>
2023-10-16 15:14:48 +00:00
Gert Wollny
3fae614286 r600/sfn: When simplifying src vec4 pinnings, also check all uses
If a value would be used e.g. as Rn.x___ and also as Rn.xy__, in two
different instructions , then the first use was removing the group
property if Rn.x, which then broke the use in the second case, because
RA didn't see anymore, that Rn.x and Rn.y must be allocated with the
same register ID "n".

Fixes: c23604324b (r600/sfn: copy-propagate single source texture values)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9998

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25741>
2023-10-16 14:21:01 +00:00
Gert Wollny
e9c21952aa r600/sfn: Don't override a chgr pinning during copy propagation
Fixes: c0b6c59e0 (r600/sfn: Copy propagate into TEX source)
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9998

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25741>
2023-10-16 14:21:01 +00:00
Faith Ekstrand
7fb561eff2 vulkan/wsi: Allow for larger linear images
For images of size 32768 × 32768 (which NVK allows), the linear image
ends up being 4GB which overflows the uint32_t size as well as some of
our alignment calculations.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25729>
2023-10-16 13:02:14 +00:00
Faith Ekstrand
7a83109835 nvk: Clean up the disk cache on physical device create fail path
Fixes: a4f8fd9dd5 ("nvk: Hook up the disk cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25749>
2023-10-16 05:58:58 -05:00
Faith Ekstrand
922e6e5423 nvk: Handle unbinding images and buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25747>
2023-10-16 09:40:59 +00:00
Faith Ekstrand
0c84c55972 nvk: Add an nvk_shader_finish() helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25747>
2023-10-16 09:40:59 +00:00
Faith Ekstrand
112be1901b nvk: Free the disk cache
Fixes: a4f8fd9dd5 ("nvk: Hook up the disk cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25747>
2023-10-16 09:40:59 +00:00
Faith Ekstrand
16725e4d70 nvk: Use nouveau_ws_bo_unmap() instead of munmap()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25747>
2023-10-16 09:40:59 +00:00
Hannes Mann
7881874847 vulkan/wsi/wayland: Fix detection of tearing control protocol
Fixes: 5ceba97c2e ("vulkan/wsi/wayland: add support for IMMEDIATE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25689>
2023-10-16 09:06:24 +00:00
Eric Engestrom
042d256c1e util/xmlconfig: inline datadir
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21808>
2023-10-16 07:59:38 +00:00
Eric Engestrom
44b0764930 util/xmlconfig: drop driInjectDataDir() now that DRIRC_CONFIGDIR is always supported
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21808>
2023-10-16 07:59:38 +00:00
Erik Faye-Lund
128c2bdf73 meson: add src/util to the drirc search path
With this, we pick up new in-tree defaults for driconfig variables
when using meson devenv. This is useful for testing new config
variables.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21808>
2023-10-16 07:59:38 +00:00
Erik Faye-Lund
6c5a9ede64 util/xmlconfig: add an env-var for overriding drirc search dir
This adds an environment variable that can be used to override the
global drirc serach directory. This can be useful for debugging, and
meson devenv, as used in the following commit.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21808>
2023-10-16 07:59:38 +00:00
Karol Herbst
ccdea7bbeb rusticl/format: disable all sRGB formats
Fixes: 714e11fe04 ("rusticl/format: enable all trivial to support optional image formats")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25739>
2023-10-15 21:28:15 +00:00
Karol Herbst
bdd255bd04 rusticl/memory: use PIPE_BUFFER for IMAGE1D_BUFFER images
Fixes samplerless 1Dbuffer tests with Zink.

Fixes: 20c90fed5a ("rusticl: added")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25739>
2023-10-15 21:28:15 +00:00
Karol Herbst
e79d9a9cc8 rusticl/device: restrict 1Dbuffer images for RGB and RGBx
Fixes: 20c90fed5a ("rusticl: added")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25739>
2023-10-15 21:28:15 +00:00