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ac/gpu_info: split ib_alignment as ip[type].ib_alignment
No change in behavior. The previous overalignment is preserved. It sets ib_pad_dw_mask sooner. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25578>
This commit is contained in:
Marek Olšák
Marge Bot
parent
cba898a530
commit
e0813c5477
6 changed files with 48 additions and 43 deletions
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@ -647,6 +647,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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return false;
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}
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unsigned max_ib_alignment = 0;
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for (unsigned ip_type = 0; ip_type < AMD_NUM_IP_TYPES; ip_type++) {
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struct drm_amdgpu_info_hw_ip ip_info = {0};
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@ -677,10 +679,26 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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info->ip[AMD_IP_GFX].ver_minor = info->ip[AMD_IP_COMPUTE].ver_minor = 3;
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}
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info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
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info->ib_alignment = MAX3(info->ib_alignment, ip_info.ib_start_alignment,
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ip_info.ib_size_alignment);
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info->ip[ip_type].ib_alignment = MAX2(ip_info.ib_start_alignment, ip_info.ib_size_alignment);
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max_ib_alignment = MAX2(max_ib_alignment, info->ip[ip_type].ib_alignment);
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}
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/* TODO: Remove this. This hack mimics the previous behavior of global ib_alignment. */
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for (unsigned ip_type = 0; ip_type < AMD_NUM_IP_TYPES; ip_type++) {
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info->ip[ip_type].ib_alignment = MAX2(max_ib_alignment, 1024);
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}
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/* This is "align_mask" copied from the kernel, maximums of all IP versions. */
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info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff;
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info->ib_pad_dw_mask[AMD_IP_COMPUTE] = 0xff;
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info->ib_pad_dw_mask[AMD_IP_SDMA] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_UVD] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_VCE] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_UVD_ENC] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_VCN_DEC] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_VCN_ENC] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_VCN_JPEG] = 0xf;
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/* Only require gfx or compute. */
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if (!info->ip[AMD_IP_GFX].num_queues && !info->ip[AMD_IP_COMPUTE].num_queues) {
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fprintf(stderr, "amdgpu: failed to find gfx or compute.\n");
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@ -690,12 +708,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_COMPUTE].num_queues));
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assert(util_is_power_of_two_or_zero(info->ip[AMD_IP_SDMA].num_queues));
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/* The kernel pads gfx and compute IBs to 256 dwords since:
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* 66f3b2d527154bd258a57c8815004b5964aa1cf5
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* Do the same.
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*/
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info->ib_alignment = MAX2(info->ib_alignment, 1024);
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r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
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&info->me_fw_feature);
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if (r) {
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@ -1132,17 +1144,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
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info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;
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info->lds_alloc_granularity = info->gfx_level >= GFX10_3 ? 256 * 4 : info->lds_encode_granularity;
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/* This is "align_mask" copied from the kernel, maximums of all IP versions. */
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info->ib_pad_dw_mask[AMD_IP_GFX] = 0xff;
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info->ib_pad_dw_mask[AMD_IP_COMPUTE] = 0xff;
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info->ib_pad_dw_mask[AMD_IP_SDMA] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_UVD] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_VCE] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_UVD_ENC] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_VCN_DEC] = 0xf;
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info->ib_pad_dw_mask[AMD_IP_VCN_ENC] = 0x3f;
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info->ib_pad_dw_mask[AMD_IP_VCN_JPEG] = 0xf;
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/* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
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* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
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* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
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@ -1681,8 +1682,9 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
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for (unsigned i = 0; i < AMD_NUM_IP_TYPES; i++) {
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if (info->ip[i].num_queues) {
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fprintf(f, " IP %-7s %2u.%u \tqueues:%u\n", ip_string[i],
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info->ip[i].ver_major, info->ip[i].ver_minor, info->ip[i].num_queues);
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fprintf(f, " IP %-7s %2u.%u \tqueues:%u (align:%u, pad_dw:0x%x)\n", ip_string[i],
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info->ip[i].ver_major, info->ip[i].ver_minor, info->ip[i].num_queues,
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info->ip[i].ib_alignment, info->ib_pad_dw_mask[i]);
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}
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}
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@ -1756,7 +1758,6 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
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fprintf(f, "CP info:\n");
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fprintf(f, " gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
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fprintf(f, " ib_alignment = %u\n", info->ib_alignment);
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fprintf(f, " me_fw_version = %i\n", info->me_fw_version);
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fprintf(f, " me_fw_feature = %i\n", info->me_fw_feature);
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fprintf(f, " mec_fw_version = %i\n", info->mec_fw_version);
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@ -26,6 +26,7 @@ struct amd_ip_info {
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uint8_t ver_minor;
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uint8_t ver_rev;
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uint8_t num_queues;
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uint32_t ib_alignment;
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};
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struct radeon_info {
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@ -160,7 +161,6 @@ struct radeon_info {
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/* CP info. */
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bool gfx_ib_pad_with_type2;
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unsigned ib_alignment; /* both start and size alignment */
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uint32_t me_fw_version;
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uint32_t me_fw_feature;
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uint32_t mec_fw_version;
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@ -140,9 +140,9 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout, struct
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}
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static uint32_t
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radv_align_cmdbuf_size(const struct radv_device *device, uint32_t size)
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radv_align_cmdbuf_size(const struct radv_device *device, uint32_t size, enum amd_ip_type ip_type)
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{
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const uint32_t ib_alignment = device->physical_device->rad_info.ib_alignment;
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const uint32_t ib_alignment = device->physical_device->rad_info.ip[ip_type].ib_alignment;
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return align(size, ib_alignment);
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}
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@ -150,7 +150,7 @@ radv_align_cmdbuf_size(const struct radv_device *device, uint32_t size)
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static unsigned
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radv_dgc_preamble_cmdbuf_size(const struct radv_device *device)
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{
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return radv_align_cmdbuf_size(device, 16);
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return radv_align_cmdbuf_size(device, 16, AMD_IP_GFX);
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}
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static bool
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@ -173,7 +173,7 @@ radv_get_indirect_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
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uint32_t cmd_size, upload_size;
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radv_get_sequence_size(layout, pipeline, &cmd_size, &upload_size);
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return radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount);
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return radv_align_cmdbuf_size(device, cmd_size * cmd_info->sequencesCount, AMD_IP_GFX);
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}
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struct radv_dgc_params {
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@ -474,7 +474,7 @@ dgc_cmd_buf_size(nir_builder *b, nir_def *sequence_count, const struct radv_devi
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nir_def *cmd_buf_size = load_param32(b, cmd_buf_size);
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nir_def *cmd_buf_stride = load_param32(b, cmd_buf_stride);
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nir_def *size = nir_imul(b, cmd_buf_stride, sequence_count);
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unsigned align_mask = radv_align_cmdbuf_size(device, 1) - 1;
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unsigned align_mask = radv_align_cmdbuf_size(device, 1, AMD_IP_GFX) - 1;
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size = nir_iand_imm(b, nir_iadd_imm(b, size, align_mask), ~align_mask);
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@ -1367,12 +1367,14 @@ radv_GetGeneratedCommandsMemoryRequirementsNV(VkDevice _device,
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uint32_t cmd_stride, upload_stride;
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radv_get_sequence_size(layout, pipeline, &cmd_stride, &upload_stride);
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VkDeviceSize cmd_buf_size =
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radv_align_cmdbuf_size(device, cmd_stride * pInfo->maxSequencesCount) + radv_dgc_preamble_cmdbuf_size(device);
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VkDeviceSize cmd_buf_size = radv_align_cmdbuf_size(device, cmd_stride * pInfo->maxSequencesCount, AMD_IP_GFX) +
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radv_dgc_preamble_cmdbuf_size(device);
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VkDeviceSize upload_buf_size = upload_stride * pInfo->maxSequencesCount;
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pMemoryRequirements->memoryRequirements.memoryTypeBits = device->physical_device->memory_types_32bit;
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pMemoryRequirements->memoryRequirements.alignment = device->physical_device->rad_info.ib_alignment;
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pMemoryRequirements->memoryRequirements.alignment =
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MAX2(device->physical_device->rad_info.ip[AMD_IP_GFX].ib_alignment,
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device->physical_device->rad_info.ip[AMD_IP_COMPUTE].ib_alignment);
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pMemoryRequirements->memoryRequirements.size =
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align(cmd_buf_size + upload_buf_size, pMemoryRequirements->memoryRequirements.alignment);
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}
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@ -1506,7 +1508,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
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radv_get_sequence_size(layout, pipeline, &cmd_stride, &upload_stride);
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unsigned cmd_buf_size =
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radv_align_cmdbuf_size(cmd_buffer->device, cmd_stride * pGeneratedCommandsInfo->sequencesCount);
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radv_align_cmdbuf_size(cmd_buffer->device, cmd_stride * pGeneratedCommandsInfo->sequencesCount, AMD_IP_GFX);
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uint64_t upload_addr =
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radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
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@ -248,7 +248,7 @@ radv_amdgpu_cs_bo_create(struct radv_amdgpu_cs *cs, uint32_t ib_size)
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const enum radeon_bo_flag flags =
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RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | gtt_wc_flag;
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return ws->buffer_create(ws, ib_size, cs->ws->info.ib_alignment, domain, flags, RADV_BO_PRIORITY_CS, 0,
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return ws->buffer_create(ws, ib_size, cs->ws->info.ip[cs->hw_ip].ib_alignment, domain, flags, RADV_BO_PRIORITY_CS, 0,
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&cs->ib_buffer);
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}
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@ -287,7 +287,7 @@ radv_amdgpu_cs_get_new_ib(struct radeon_cmdbuf *_cs, uint32_t ib_size)
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static unsigned
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radv_amdgpu_cs_get_initial_size(struct radv_amdgpu_winsys *ws, enum amd_ip_type ip_type)
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{
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const uint32_t ib_alignment = ws->info.ib_alignment;
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const uint32_t ib_alignment = ws->info.ip[ip_type].ib_alignment;
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assert(util_is_power_of_two_nonzero(ib_alignment));
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return align(20 * 1024 * 4, ib_alignment);
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}
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@ -377,7 +377,7 @@ radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
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return;
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}
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const uint32_t ib_alignment = cs->ws->info.ib_alignment;
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const uint32_t ib_alignment = cs->ws->info.ip[cs->hw_ip].ib_alignment;
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cs->ws->base.cs_finalize(_cs);
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@ -1669,7 +1669,7 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_request
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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ib = &request->ibs[i];
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assert(ib->ib_mc_address && ib->ib_mc_address % ctx->ws->info.ib_alignment == 0);
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assert(ib->ib_mc_address && ib->ib_mc_address % ctx->ws->info.ip[ib->ip_type].ib_alignment == 0);
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assert(ib->size);
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chunk_data[i].ib_data._pad = 0;
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@ -951,11 +951,11 @@ static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib)
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}
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static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs,
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struct amdgpu_ib *ib)
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struct amdgpu_ib *ib, enum amd_ip_type ip_type)
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{
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amdgpu_set_ib_size(rcs, ib);
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ib->used_ib_space += rcs->current.cdw * 4;
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ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_alignment);
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ib->used_ib_space = align(ib->used_ib_space, ws->info.ip[ip_type].ib_alignment);
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ib->max_ib_size = MAX2(ib->max_ib_size, rcs->prev_dw + rcs->current.cdw);
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}
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@ -1145,12 +1145,12 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
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struct amdgpu_cs *cs = amdgpu_cs(rcs);
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struct amdgpu_winsys *ws = cs->ws;
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struct amdgpu_cs_context *csc[2] = {&cs->csc1, &cs->csc2};
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unsigned size = align(preamble_num_dw * 4, ws->info.ib_alignment);
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unsigned size = align(preamble_num_dw * 4, ws->info.ip[AMD_IP_GFX].ib_alignment);
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struct pb_buffer *preamble_bo;
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uint32_t *map;
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/* Create the preamble IB buffer. */
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preamble_bo = amdgpu_bo_create(ws, size, ws->info.ib_alignment,
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preamble_bo = amdgpu_bo_create(ws, size, ws->info.ip[AMD_IP_GFX].ib_alignment,
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RADEON_DOMAIN_VRAM,
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RADEON_FLAG_NO_INTERPROCESS_SHARING |
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RADEON_FLAG_GTT_WC |
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@ -1708,7 +1708,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
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if (noop && acs->ip_type == AMD_IP_GFX) {
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/* Reduce the IB size and fill it with NOP to make it like an empty IB. */
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unsigned noop_size = MIN2(cs->ib[IB_MAIN].ib_bytes, ws->info.ib_alignment);
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unsigned noop_size = MIN2(cs->ib[IB_MAIN].ib_bytes, ws->info.ip[AMD_IP_GFX].ib_alignment);
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cs->ib_main_addr[0] = PKT3(PKT3_NOP, noop_size / 4 - 2, 0);
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cs->ib[IB_MAIN].ib_bytes = noop_size;
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@ -1862,7 +1862,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
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struct amdgpu_cs_context *cur = cs->csc;
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/* Set IB sizes. */
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amdgpu_ib_finalize(ws, rcs, &cs->main);
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amdgpu_ib_finalize(ws, rcs, &cs->main, cs->ip_type);
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/* Create a fence. */
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amdgpu_fence_reference(&cur->fence, NULL);
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@ -544,6 +544,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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}
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}
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for (unsigned ip_type = 0; ip_type < AMD_NUM_IP_TYPES; ip_type++)
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ws->info.ip[ip_type].ib_alignment = 4096;
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/* Hawaii with old firmware needs type2 nop packet.
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* accel_working2 with value 3 indicates the new firmware.
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*/
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@ -551,7 +554,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
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(ws->info.family == CHIP_HAWAII &&
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ws->accel_working2 < 3);
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ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
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ws->info.ib_alignment = 4096;
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ws->info.has_bo_metadata = false;
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ws->info.has_eqaa_surface_allocator = false;
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ws->info.has_sparse_vm_mappings = false;
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