Commit graph

64798 commits

Author SHA1 Message Date
Matt Turner
cc60a487d1 i965/fs: Optimize emit_bool_to_cond_code for logical exprs.
AND, OR, and XOR can generate the conditional code directly.

total instructions in shared programs: 4293335 -> 4292303 (-0.02%)
instructions in affected programs:     121408 -> 120376 (-0.85%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-18 18:35:53 -07:00
Matt Turner
2a6b6621d8 i965: Use UniformBooleanTrue value for boolean literal true.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-18 18:35:49 -07:00
Matt Turner
9e2e7c7dc0 glsl: Use UniformBooleanTrue value for uniform initializers.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-18 18:35:48 -07:00
Matt Turner
6df0fd8fe9 mesa: Upload boolean uniforms using UniformBooleanTrue.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-18 18:35:47 -07:00
Matt Turner
e0f955abd3 i965: Remove dead call to _mesa_associate_uniform_storage().
Dead since the call to _mesa_generate_parameters_list_for_uniforms
was removed in commit 12751ef2. So this was why all of that code that
was supposed to fix up the value of a uniform bool to wasn't happening.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-08-18 18:35:41 -07:00
Matt Turner
e87106d153 mapi: Inline shared-glapi/tests/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-18 18:27:20 -07:00
Matt Turner
7172f02d7c mapi: Inline glapi/tests/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-18 18:27:16 -07:00
Matt Turner
9dbb0f49b6 mapi: Inline glapi/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-18 18:25:52 -07:00
Matt Turner
dff5a219d0 mapi: Inline es2api/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-18 18:25:29 -07:00
Matt Turner
18ef5136b6 mapi: Inline es1api/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-18 18:25:02 -07:00
Matt Turner
c3ce1a942f mapi: Inline shared-glapi/Makefile. 2014-08-18 18:24:09 -07:00
Matt Turner
4ccd2a9f9b build: Let install-lib-links.mk handle .la files in subdirectories.
The next patches are going to combine some of the mapi subdirectories'
Makefiles into a single Makefile, giving better build parallelism.

lib_LTLIBRARIES will be set to something like

   lib_LTLIBRARIES = shared-glapi/libglapi.la es2api/libGLESv2.la

and the current code in install-lib-links.mk simply prepends .libs/ and
replaces the .la in order to create the filenames that it needs to ln/cp
into the LIBDIR. This doesn't work when the .la file is actually in a
subdirectory.

This patch fixes this and puts .libs/ in the right place.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-18 18:22:40 -07:00
Matt Turner
45eb065668 i965: Enable instruction compaction on Gen8+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
31eed95b22 i965: Add support for compacting 3-src instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
fb1db6753f i965: Add support for compacting 1- and 2-src instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
3904d404a3 i965/gen8: Add 3-src instruction compaction tables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
190ce6b093 i965/gen8: Add instruction compaction tables.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
2faa1a414c i965: Update JIP/UIP compaction code to operate on bytes.
JIP/UIP were previously in units of compacted instructions. On Gen8
they're in units of bytes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
23ab55cb6c i965: Reverse condition ordering to let us support other gens.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-18 18:18:50 -07:00
Matt Turner
6cc6c3b647 i965/disasm: Add CSEL. 2014-08-18 18:18:50 -07:00
Timothy Arceri
39a920c0cb mesa: fix copy and paste errors in glBindVertexBuffers
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
2014-08-19 10:19:18 +10:00
Tobias Klausmann
9100c359ac nv50/ir: (trivial) initialize pointer to silence warning
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
2014-08-18 19:41:26 -04:00
Eric Anholt
76f687d5a5 vc4: Add support for swizzling of texture colors.
Fixes swapped colors on the copypix demo and some piglit tests like
pbo-teximage-tiling .
2014-08-18 15:27:43 -07:00
Eric Anholt
489350e570 vc4: Fix handling of non-XYZW swizzles in color outputs.
The SWIZZLE_1 of the winsys destination was dereffing off the end of the
array, which surprisingly often worked out (since nobody reads the
rendered value anyway, so whatever junk was referenced in the QIR didn't
matter), but shader dumping would sometimes segfault.
2014-08-18 15:27:43 -07:00
Eric Anholt
37992a4e39 vc4: Extract the swizzle handling from vertex fetch.
I want to reuse this elsewhere, and NONE debug output hasn't been useful
so I don't miss it being as detailed as it was before.
2014-08-18 15:27:43 -07:00
Eric Anholt
c1db622215 vc4: Add support for color masking.
This gets fbo-colormask-formats working for core formats, which increases
my confidence in some of the swizzle and blend handling.
2014-08-18 15:27:43 -07:00
Eric Anholt
50b4293eb3 vc4: Add a helper for QOP_R4_UNPACK_[ABCD]. 2014-08-18 15:27:43 -07:00
Eric Anholt
8795341e2c vc4: Don't forget to set up the offset for render targets.
This almost fixes fbo-generatemipmap rendering, except that the 1x1 level
isn't getting rendered.
2014-08-18 15:27:43 -07:00
Eric Anholt
63fe494877 vc4: Fix multi-level texture setup.
We weren't accounting for the level 0 offset in the texture setup (so it
only worked if it happened to be a single-level texture), and doing so
required that we get the level 0 offset page aligned so that the offset
bits don't get interpreted as the texture format and such.
2014-08-18 15:27:43 -07:00
Eric Anholt
a538bab065 vc4: Fix viewport handling in the uniforms upload.
I had the right viewports in vc4_emit.c, but grabbed the wrong values in
the uniform setup, so primitives would claim to be in the wrong parts of
the screen.  (The vc4_emit.c state looks like it just decides how big the
clipping guardband is).

This gets fbo-viewport closer to working (which still has the problem that
the HW is always guard-band clipping), and fixes inverted FBO rendering in
general.
2014-08-18 15:27:43 -07:00
Marek Olšák
082d8c54c1 docs/relnotes: document GLX_MESA_query_renderer 2014-08-19 00:26:41 +02:00
Francisco Jerez
e9a4e74926 clover: Refuse to build a program if there are kernel objects attached to it.
Fixes piglit cl-api-build-program.

Tested-by: EdB <edb+mesa@sigluy.net>
2014-08-18 09:32:24 +03:00
Francisco Jerez
c6817f19f6 clover/util: Pass initial count value to ref_counter constructor.
And mark the ref_count() method as const.

Tested-by: EdB <edb+mesa@sigluy.net>
2014-08-18 09:32:24 +03:00
Francisco Jerez
37e4d22e95 clover/util: Implement minimalist reference to clover::ref_counter object.
Tested-by: EdB <edb+mesa@sigluy.net>
2014-08-18 09:32:24 +03:00
EdB
ce4d3f3104 clover: clGetProgramInfo support for OpenCL 1.2.
[ Francisco Jerez: Rework using fold() for conciseness. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: EdB <edb+mesa@sigluy.net>
2014-08-17 23:34:11 +03:00
Ilia Mirkin
ef130b6050 nouveau: don't keep stale pointer to free'd data
If ->sys is non-null, we might decide that it's where the data is
stored.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
2014-08-16 17:52:54 -04:00
Ilia Mirkin
1f4bc0c95e egl: don't exit process on initialization failure
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-08-16 17:52:54 -04:00
Brian Paul
9d9879abed mesa: fix compressed_subtexture_error_check() return value
The function should return GLboolean, not GLenum.
If we detect invalid compressed pixel storage parameters, we should
return GL_TRUE, not GL_FALSE so that the function is no-op'd.
An update to the piglit s3tc-errors test will check this.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 06:48:45 -06:00
Brian Paul
cf8b680f40 mesa: move _mesa_compressed_texture_pixel_storage_error_check()
to pixelstore.c, add const qualifier to the 'packing' parameter.
Add comments.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 06:48:44 -06:00
Brian Paul
9b4c6da7f0 mesa: minor improvements to _mesa_compute_compressed_pixelstore()
Replace the gl_texture_image parameter with mesa_format since we only
used the image's format.

Add some comments.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-16 06:48:44 -06:00
Brian Paul
1e594d4f5c util: whitespace and formatting fixes in u_math.h
Trivial.
2014-08-16 06:48:44 -06:00
Ilia Mirkin
8867ffbf95 nouveau: make sure to invalidate any vbo state as well
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
2014-08-16 02:33:12 -04:00
Jordan Justen
a1dca7069b i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hiz
For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for
separate stencil/hiz. This is needed because gen6 hiz and separate
stencil only support a single miplevel. When accessing the other LODs,
we will program a tile aligned offset for the bo.

PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
 "The separate stencil buffer does not support mip mapping, thus the
  storage for LODs other than LOD 0 is not needed."

We still allocate storage for the other stencil mip-levels within a
single texture, but each mip-level will use non-mip-array spacing.

PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
 "[DevSNB]: The hierarchical depth buffer does not support the LOD
  field, it is assumed by hardware to be zero. A separate
  hierarachical depth buffer is required for each LOD used, and the
  corresponding buffer’s state delivered to hardware each time a new
  depth buffer state with modified LOD is delivered."

We allocate storage for the other hiz mip-levels within a single
texture, but each mip-level will use non-mip-array spacing.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:42 -07:00
Jordan Justen
31e1beec89 i965/gen6: Stencil/hiz needs an offset for LOD > 0
Since gen6 separate stencil & hiz only supports LOD0, we need to
program an offset to the LOD when emitting the separate stencil/hiz.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:42 -07:00
Jordan Justen
b3d68d5a30 i965/gen6: Force tile alignment for each stencil/hiz LOD
Gen6 doesn't support multiple miplevels for hiz and stencil.

Therefore, we must point to the LOD directly during rendering.

But, we also have removed the tile offsets from normal depth surfaces,
so we need to align each LOD to a tile boundary for hiz and stencil.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:42 -07:00
Jordan Justen
6345a94a9b i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODs
Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array
spacing lod0 on gen7+ and therefore was only used with a single mip
level.

gen6 separate stencil & hiz only support LOD0, so we need to allocate
the miptree similar to gen7+ array spacing lod0, except we also need
space for multiple mip levels. (Since OpenGL stencil and depth support
multiple LODs.)

The miptree is allocated with tightly packed array slice spacing, but
we still also pack the miplevels into the region similar to a normal
multi mip level packing.

A 2D Array texture with 2 slices and multiple LODs would look somewhat
like this:

+----------+
|          |
|          |
+----------+
|          |
|          |
+----------+
+---+ +-+
|   | +-+
+---+ +-+
|   | :
+---+

v3:
 * Use new array_layout enum
 * ASCII art!

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:41 -07:00
Jordan Justen
27f5fa7a37 i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD
gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:41 -07:00
Jordan Justen
7e856d0b18 i965: Change mipmap array_spacing_lod0 to array_layout (enum)
We will want to setup gen6 separate stencil and hiz miptrees in a
layout that is similar to array_spacing_lod0. This is needed because
gen6 hiz and stencil only support a single mip-level.

In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz),
the array slices will be packed at each LOD without reserving extra
space for LODs within each array slice.

So, we generalize the name of this field and add comments to indicate
the old and new uses.

Motivation for the gen6 change comes from the PRM:

PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
 "The separate stencil buffer does not support mip mapping, thus the
  storage for LODs other than LOD 0 is not needed."

PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
 "[DevSNB]: The hierarchical depth buffer does not support the LOD
  field, it is assumed by hardware to be zero. A separate
  hierarachical depth buffer is required for each LOD used, and the
  corresponding buffer’s state delivered to hardware each time a new
  depth buffer state with modified LOD is delivered."

v2:
 * Rename array_spacing_lod0 to non_mip_arrays
v3:
 * Instead, replace array_spacing_lod0 with array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:41 -07:00
Jordan Justen
56cdb55e38 i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
(bf25ee2 for gen6)

Previously we would always find the 2D sub-surface of interest,
and then program the surface to this location. Now we always
program the 3DSTATE_DEPTH_BUFFER at the start of the surface.
To select the lod/slice, we utilize the lod & minimum array
element fields.

We also must disable brw_workaround_depthstencil_alignment for
gen >= 6. Now the hardware will handle alignment when rendering
to additional slices/LODs.

v3:
 * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:41 -07:00
Jordan Justen
3da13aef01 i965/gen6 fbo: make unmatched depth/stencil configs return unsupported
(f3c886b for gen6)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-15 20:11:41 -07:00