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Samuel Pitoiset
cb9c25cbea radv: rename radv_flush_occlusion_query_state() 
To match other emit functions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37141>
 2025-09-05 09:21:21 +00:00
Lionel Landwerlin
07039cdb3d anv: fixup robust_ubo_range mask
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c7e48f79b7 ("brw,anv: Reduce UBO robustness size alignment to 16 bytes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13834
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37183>
 2025-09-05 08:56:47 +00:00
Hans-Kristian Arntzen
fa486a0346 anti-lag: Fix stype for submit2 semaphores. 
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 722ffe9a73 ("vulkan: implement VK_AMD_anti_lag as implicit vulkan layer")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37159>
 2025-09-05 08:14:28 +00:00
Lionel Landwerlin
d8add9866b anv: add an undocumented HW workaround for Gfx12.5 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:21 +00:00
Lionel Landwerlin
4314c891f4 anv: expose VK_EXT_shader_object 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:21 +00:00
Lionel Landwerlin
1de9f367e8 anv: remove unused gfx/compute pipeline code 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:20 +00:00
Lionel Landwerlin
e76ed91d3f anv: switch over to runtime pipelines 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:20 +00:00
Lionel Landwerlin
4d9dd5c3a2 anv: store a few default instructions 
We will use those where no associated shaders is active but we still
need some default values programmed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:20 +00:00
Lionel Landwerlin
69b6b4cb28 anv: add shader instruction emission 
Should replace much of genX_pipeline.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:19 +00:00
Lionel Landwerlin
8f4c2bd566 anv: add runtime shader statistic support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:19 +00:00
Lionel Landwerlin
91abb0e0af anv: move internal RT shaders around 
anv_pipeline.c is about to go.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:18 +00:00
Lionel Landwerlin
d39e443ef8 anv: add infrastructure for common vk_pipeline 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:18 +00:00
Lionel Landwerlin
7cbabcad36 compiler: add stage_is_graphics() helper 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:17 +00:00
Lionel Landwerlin
50fd669294 anv: prep work for separate tessellation shaders 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:17 +00:00
Lionel Landwerlin
a91e0e0d61 brw: add support for separate tessellation shader compilation 
Tessellation factors have to be written dynamically (based on the next
shader primitive topology) and the builtins read using a dynamic
offset (based on the preceeding shader's VUE).

Anv is updated to use this new infrastructure for dynamic
patch_control_points.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:17 +00:00
Lionel Landwerlin
a18835a9ca anv/brw/iris: move VS VUE computation to backend 
Drivers can provide the inputs required for the backend to call the
compute function.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:16 +00:00
Lionel Landwerlin
8dee4813b0 brw: add ability to compute VUE map for separate tcs/tes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:16 +00:00
Lionel Landwerlin
afea98593e nir: add a new intrinsic for load dynamic tessellation config 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
 2025-09-05 07:46:15 +00:00
Samuel Pitoiset
7f12f98741 radv: rework the optimal packet order for dispatches 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:14 +00:00
Samuel Pitoiset
62c92a0516 radv: rework the optimal packet order for task/mesh draws 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:13 +00:00
Samuel Pitoiset
f5bbe5228f radv: rework the optimal packet order for "normal" draws 
This idea comes from RadeonSI but RADV was already implementing
something similar. Except that it checked for wait-for-idle but this
shouldn't be necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37013>
 2025-09-05 07:28:12 +00:00
Samuel Pitoiset
f289e8eddc radv: only expose permitted global queue priorities
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It's the responsability of the application to check for
VK_ERROR_NOT_PERMITTED, but filtering not permitted priorities seems
better.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13775
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37076>
 2025-09-05 06:34:36 +00:00
Samuel Pitoiset
43cba046e6 radv/amdgpu: add a function to query permitted context priorities 
The only way I know of is to create a context to verify if a priority
is permitted or not.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37076>
 2025-09-05 06:34:36 +00:00
Samuel Pitoiset
57deff5658 radv: fix vk_error in radv_update_preambles() 
This needs to be a vk object, otherwise it asserts or crashes.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37179>
 2025-09-05 06:14:49 +00:00
Samuel Pitoiset
44541e84e9 radv: move misc related drirc to radv_drirc::misc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:17 +00:00
Samuel Pitoiset
8e4d5743d2 radv: move debug related drirc to radv_drirc::debug 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:17 +00:00
Samuel Pitoiset
f13b181791 radv: move performance related drirc to radv_drirc::performance 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:16 +00:00
Samuel Pitoiset
d575b91b3a radv: move features related drirc to radv_drirc::features 
For better organization.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:16 +00:00
Samuel Pitoiset
d915f24cb2 radv: move drirc options to a separate struct 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:15 +00:00
Samuel Pitoiset
d98e31eab6 radv: mark RADV_DEBUG=nongg_gs as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:15 +00:00
Samuel Pitoiset
7304423b5c radv: mark RADV_DEBUG=splitfma as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:14 +00:00
Samuel Pitoiset
4748ecb238 radv: mark RADV_DEBUG=invariantgeom as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:13 +00:00
Samuel Pitoiset
a8a8bfee1f radv: mark RADV_DEBUG=nodynamicbounds as deprecated 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37145>
 2025-09-05 05:56:13 +00:00
Ian Romanick
1ce90ad5e1 elk: Use nir_opt_sink and more nir_opt_move
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I spent a bunch of time playing around with the various enable bits, and
this was the best I could come up with. Enabling any of
nir_move_comparisons or nir_move_load_ubo in nir_opt_sink helped
instructions quite a bit, but it also caused a large pile of added
spills and fills.

shader-db:

Broadwell
total instructions in shared programs: 18428980 -> 18427957 (<.01%)
instructions in affected programs: 425245 -> 424222 (-0.24%)
helped: 1522 / HURT: 405

total cycles in shared programs: 954756705 -> 953755695 (-0.10%)
cycles in affected programs: 623470486 -> 622469476 (-0.16%)
helped: 17989 / HURT: 21175

total spills in shared programs: 8349 -> 8356 (0.08%)
spills in affected programs: 285 -> 292 (2.46%)
helped: 7 / HURT: 13

total fills in shared programs: 10426 -> 10192 (-2.24%)
fills in affected programs: 675 -> 441 (-34.67%)
helped: 25 / HURT: 1

LOST:   346
GAINED: 554

Haswell
total instructions in shared programs: 16809730 -> 16801634 (-0.05%)
instructions in affected programs: 772251 -> 764155 (-1.05%)
helped: 3055 / HURT: 840

total cycles in shared programs: 945179935 -> 944315696 (-0.09%)
cycles in affected programs: 549177588 -> 548313349 (-0.16%)
helped: 34143 / HURT: 23605

total spills in shared programs: 7699 -> 7666 (-0.43%)
spills in affected programs: 353 -> 320 (-9.35%)
helped: 10 / HURT: 16

total fills in shared programs: 8184 -> 7671 (-6.27%)
fills in affected programs: 1006 -> 493 (-50.99%)
helped: 30 / HURT: 2

total sends in shared programs: 1016676 -> 1016682 (<.01%)
sends in affected programs: 49 -> 55 (12.24%)
helped: 0 / HURT: 6

LOST:   415
GAINED: 441

Ivy Bridge
total instructions in shared programs: 15764955 -> 15757178 (-0.05%)
instructions in affected programs: 707453 -> 699676 (-1.10%)
helped: 2893 / HURT: 547

total cycles in shared programs: 430017934 -> 429720104 (-0.07%)
cycles in affected programs: 251816726 -> 251518896 (-0.12%)
helped: 33110 / HURT: 22056

total spills in shared programs: 1537 -> 1525 (-0.78%)
spills in affected programs: 18 -> 6 (-66.67%)
helped: 6 / HURT: 0

total fills in shared programs: 926 -> 905 (-2.27%)
fills in affected programs: 24 -> 3 (-87.50%)
helped: 6 / HURT: 0

total sends in shared programs: 816646 -> 816652 (<.01%)
sends in affected programs: 49 -> 55 (12.24%)
helped: 0 / HURT: 6

LOST:   332
GAINED: 417

Sandy Bridge
total instructions in shared programs: 14055229 -> 14045281 (-0.07%)
instructions in affected programs: 1436142 -> 1426194 (-0.69%)
helped: 5858 / HURT: 757

total cycles in shared programs: 772123170 -> 813543451 (5.36%)
cycles in affected programs: 521342483 -> 562762764 (7.94%)
helped: 27928 / HURT: 35923

total spills in shared programs: 1742 -> 1741 (-0.06%)
spills in affected programs: 66 -> 65 (-1.52%)
helped: 1 / HURT: 0

total fills in shared programs: 970 -> 967 (-0.31%)
fills in affected programs: 93 -> 90 (-3.23%)
helped: 1 / HURT: 0

total sends in shared programs: 1239222 -> 1238992 (-0.02%)
sends in affected programs: 6137 -> 5907 (-3.75%)
helped: 342 / HURT: 112

LOST:   244
GAINED: 434

Iron Lake and GM45 had similar results. (Iron Lake shown)
total instructions in shared programs: 8366385 -> 8363954 (-0.03%)
instructions in affected programs: 162761 -> 160330 (-1.49%)
helped: 600 / HURT: 195

total cycles in shared programs: 248992618 -> 252119334 (1.26%)
cycles in affected programs: 50774708 -> 53901424 (6.16%)
helped: 3435 / HURT: 5131

total sends in shared programs: 623693 -> 623681 (<.01%)
sends in affected programs: 351 -> 339 (-3.42%)
helped: 12 / HURT: 0

LOST: 0
GAINED: 6

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25463>
 2025-09-04 15:01:18 -07:00
Ian Romanick
6f30cf71fe brw: Use nir_opt_sink and more nir_opt_move 
The shader-db results on most platforms are pretty mixed. However, this
seems to be a decent improvement in fossil-db.

shader-db::

Lunar Lake
total instructions in shared programs: 17019147 -> 17023017 (0.02%)
instructions in affected programs: 1200847 -> 1204717 (0.32%)
helped: 814 / HURT: 2458

total cycles in shared programs: 880532116 -> 880406462 (-0.01%)
cycles in affected programs: 798253846 -> 798128192 (-0.02%)
helped: 30064 / HURT: 33008

total spills in shared programs: 3262 -> 3260 (-0.06%)
spills in affected programs: 66 -> 64 (-3.03%)
helped: 1 / HURT: 2

total fills in shared programs: 1616 -> 1637 (1.30%)
fills in affected programs: 89 -> 110 (23.60%)
helped: 1 / HURT: 2

LOST:   241
GAINED: 356

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19859724 -> 19865383 (0.03%)
instructions in affected programs: 2166810 -> 2172469 (0.26%)
helped: 942 / HURT: 3563

total cycles in shared programs: 879095859 -> 878616086 (-0.05%)
cycles in affected programs: 753840990 -> 753361217 (-0.06%)
helped: 33442 / HURT: 35053

total spills in shared programs: 4679 -> 4677 (-0.04%)
spills in affected programs: 80 -> 78 (-2.50%)
helped: 1 / HURT: 2

total fills in shared programs: 4113 -> 4175 (1.51%)
fills in affected programs: 87 -> 149 (71.26%)
helped: 1 / HURT: 2

LOST:   706
GAINED: 563

Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20610947 -> 20615741 (0.02%)
instructions in affected programs: 2138334 -> 2143128 (0.22%)
helped: 979 / HURT: 3635

total cycles in shared programs: 863103771 -> 862153697 (-0.11%)
cycles in affected programs: 731626072 -> 730675998 (-0.13%)
helped: 34060 / HURT: 34256

total spills in shared programs: 3992 -> 3949 (-1.08%)
spills in affected programs: 504 -> 461 (-8.53%)
helped: 8 / HURT: 6

total fills in shared programs: 3640 -> 3573 (-1.84%)
fills in affected programs: 1505 -> 1438 (-4.45%)
helped: 8 / HURT: 5

LOST:   622
GAINED: 1018

fossil-db:

All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 232649299 -> 232485503 (-0.07%); split: -0.16%, +0.09%
Subgroup size: 15932144 -> 15933056 (+0.01%); split: +0.01%, -0.00%
Loop count: 137431 -> 137430 (-0.00%)
Cycle count: 32619860020 -> 32714539770 (+0.29%); split: -0.80%, +1.09%
Spill count: 540835 -> 519861 (-3.88%); split: -4.79%, +0.91%
Fill count: 700278 -> 663650 (-5.23%); split: -6.46%, +1.23%
Scratch Memory Size: 37258240 -> 35654656 (-4.30%); split: -5.24%, +0.94%
Max live registers: 72561256 -> 71501759 (-1.46%); split: -1.62%, +0.16%
Non SSA regs after NIR: 67682385 -> 67692495 (+0.01%); split: -0.00%, +0.02%

Totals from 617432 (78.20% of 789594) affected shaders:
Instrs: 217754449 -> 217590653 (-0.08%); split: -0.17%, +0.10%
Subgroup size: 12656912 -> 12657824 (+0.01%); split: +0.01%, -0.00%
Loop count: 133283 -> 133282 (-0.00%)
Cycle count: 32367979192 -> 32462658942 (+0.29%); split: -0.81%, +1.10%
Spill count: 540770 -> 519796 (-3.88%); split: -4.79%, +0.91%
Fill count: 700277 -> 663649 (-5.23%); split: -6.46%, +1.23%
Scratch Memory Size: 37182464 -> 35578880 (-4.31%); split: -5.25%, +0.94%
Max live registers: 64912683 -> 63853186 (-1.63%); split: -1.81%, +0.18%
Non SSA regs after NIR: 60158776 -> 60168886 (+0.02%); split: -0.00%, +0.02%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25463>
 2025-09-04 15:01:18 -07:00
GKraats
3b5b68dbfb crocus: fix SIGSEGV crash at pbo compressed teximage 
This affects piglit/bin/ext_texture_array-compressed teximage pbo -auto -fbo

Routine create_surface() at src/gallium/drivers/crocus/crocus_state.c
does not suppport compressed format and returns NULL in that case.

Since MR https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34054
routine st_try_pbo_compressed_texsubimage() at src/mesa/state_tracker/st_cb_texture.c is missing a test via pipe->create_surface() and does
not fallback to _mesa_store_compressed_texsubimage() which causes a SIGSEGV abort.

Regression is solved by introducing the variable surface_no_compress at struct pipe_caps, causing the fallback.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13426

Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37150>
 2025-09-04 21:12:15 +00:00
Christian Gmeiner
ef55869dc8 etnaviv: Do not update derived states during non-draw force flush
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We can get into a situation where many BLT operations after a draw
cause a force flush of the current command stream. Calling
etna_state_update(..) without an active draw results in a segfault
due to inconsistent context state.

Track whether we're currently in draw_vbo to avoid updating derived
states during force flush outside of draw operations.

Passes dEQP-GLES3.functional.samplers.multi_tex_3d.* on GC7000.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36506>
 2025-09-04 19:51:16 +00:00
Gert Wollny
713edb5998 r600/sfn: handle the IF predicate in the scheduler 
This involves also emitting the CF for the blocks in the
sfn-assembler and we have to remove the special handling in the
old backend assembler.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
359bfc3138 r600/sfn: make sure that kill and update pred are not in the same group 
The two don't seem to mix well.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
6ebda9ca52 r600/sfn: extract handling of ALU_PUSH_BEFORE in assembler code 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
98b1801dc1 r600/sfn: Add method to query whether ALU block will need ALU_EXTENDED 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
8ac1342f46 r600/sfn: Drop test for address register in assembler IF predicate 
This is already handled before.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
ca1ee36516 r600/sfn: Add method to emit ALU_PUSH_BEFORE in assembler 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
fbded04e3b r600/sfn: Add method to query whether an ALU group sets the predicate 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
6cc25b15a1 r600/sfn: chain group barrier and predicate instructions 
It seems they can not be emitted in the same ALU group

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
f9ae43bf04 r600/sfn: Add a CF block start member and handle it in the tests 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
ae6b5a449a r600/sfn: Add more CF instruction types 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
a6302cf00d r600/sfn: Emit and schedule WaitACK as a separate instruction 
This is a step to emitting VTX and TEX block start instructions in the
sfn assembler instead of relying on the old backend asm code.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
a6b6ce84f7 r600/sfn: Prepare scheduler to handle WaitAck instructions 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00
Gert Wollny
b1166f3def r600/sfn: preselect fetch by using TC and VC in scheduler 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37096>
 2025-09-04 18:44:47 +00:00