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Author SHA1 Message Date
Timur Kristóf
371b1bf789 radv: Don't call nir_opt_varyings a second time when unnecessary. 
When nir_opt_varyings doesn't make progress the first time,
it should not be necessary to call it a second time.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf
403b3958c1 radv: Move preparation and fixup to separate loops in varying optimization. 
This is to stop calling nir_shader_gather_info repeatedly for
some stages, and also as a pre-requisite to the work in the next commits.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf
a98186bbf6 radv: Refactor loops in radv_graphics_shaders_link_varyings. 
No functional changes, just improved code readability.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf
1942227e73 radv: Inline radv_graphics_shaders_link_varyings_{first/second}. 
The first step of reorganizing this code.

No Fossil DB changes.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
Timur Kristóf
412af41258 radv: Add radv_foreach_stage to ForEachMacros again. 
This was lost when .clang-format was removed
from the amd folder.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
 2025-04-11 18:01:47 +00:00
David Rosca
f1f87d302f radv/video: Always enable B pictures for H264 encode
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We always allocate the extra memory needed for B pictures, so there is
no reason not to also enable B pictures always.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34449>
 2025-04-11 11:15:47 +00:00
David Rosca
a1fbaddc9c radv/video: Use ac_vcn_enc_init_cmds 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34449>
 2025-04-11 11:15:47 +00:00
David Rosca
7249d9548e radv/video: Fix encode session info for VCN3+ 
Last dword should be 0.

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34449>
 2025-04-11 11:15:47 +00:00
David Rosca
34031531fc radv/video: Fix msg header total size 
It needs to include also codec msg size.

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34449>
 2025-04-11 11:15:47 +00:00
Konstantin Seurer
b218c45973 radv: Handle nir_intrinsic_printf 
Makes it possible to use printf statements inside glsl meta shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34208>
 2025-04-10 19:31:37 +00:00
Samuel Pitoiset
2f00daf67a radv: tidy up radv_emit_hw_ngg()
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
1290b38f57 radv: tidy up radv_emit_raster_state() 
Better isolation between configuration and emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
4b2d119d90 radv: reduce the number of emitted DWORDS for MSAA 8x user sample locs 
From 24 DWORDS to 16 DWORDS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
c1ebf82700 radv: track redundant DB_RENDER_OVERRRIDE register writes on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
7f5727b313 radv: use consecutive registers for PA_SC_WINDOW_SCISSOR_{TL,BR} 
For less DWORDS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
32ea7df586 radv: move emitting more fb registers when rendering begins 
No need to delay the emission of these registers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34420>
 2025-04-10 06:56:25 +00:00
Samuel Pitoiset
001fa1cf11 radv: move the disable_trunc_coord drirc at instance/pdev level 
It no longer relies on enabled device features.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34425>
 2025-04-10 06:36:09 +00:00
Samuel Pitoiset
65d717b45a radv: remove an old workaround for D3D9 with DXVK 2.3.0 and older 
Proton 8.x+ uses this DXVK version but Proton 9.x+ is the default now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34425>
 2025-04-10 06:36:09 +00:00
Natalie Vock
916d7277c0 radv/ci: Test FP16 for GFX8
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34114>
 2025-04-09 14:21:37 +00:00
Natalie Vock
f0f4ae1713 radv: Add radv_enable_float16_gfx8 drirc and enable for Indiana Jones TGC 
This is a hard requirement from the game preventing it to start on GFX8.
Adding this allows playing it on GFX8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34114>
 2025-04-09 14:21:37 +00:00
Natalie Vock
e385cb1750 radv: Add radv_emulate_rt drirc and enable for Indiana Jones TGC 
There have been various people successfully trying it out on GFX9-GFX10.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34114>
 2025-04-09 14:21:37 +00:00
Natalie Vock
3d8db3cbbb aco: Make private_segment_buffer/scratch_offset per-resume 
We need different Temps for each resume shader, because registers aren't
preserved across resume boundaries.

This was likely fine in practice because arg registers are the same for
each shader, but resulted in invalid IR and asserts.

Fixes crashes in Indiana Jones RT with assertions enabled on GFX8.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34114>
 2025-04-09 14:21:37 +00:00
Natalie Vock
d1ff9e951a aco: Fix RT VGPR limit on Navi31/32, GFX11.5, GFX12
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Since 128 is not a multiple of the VGPR allocation granule, we will
actually allocate 134 VGPRs. No reason not to use the extra 6.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34265>
 2025-04-09 10:02:52 +00:00
Georg Lehmann
64cae5c48d aco: form mixed MTBUF/MUBUF clauses 
This should be one clause (all of the instructions load from the same vertex buffer)

s_clause 0x2                                                ; bfa10002
tbuffer_load_format_xyzw v[8:11], v5, s[4:7], 0 format:[BUF_FMT_8_8_8_8_UNORM] idxen offset:36 ; e9c32024 80010805
tbuffer_load_format_xyzw v[12:15], v5, s[4:7], 0 format:[BUF_FMT_8_8_8_8_UNORM] idxen offset:16 ; e9c32010 80010c05
tbuffer_load_format_xyzw v[16:19], v5, s[4:7], 0 format:[BUF_FMT_8_8_8_8_UNORM] idxen offset:12 ; e9c3200c 80011005
s_clause 0x2                                                ; bfa10002
buffer_load_dwordx3 v[20:22], v5, s[4:7], 0 idxen           ; e03c2000 80011405
buffer_load_dwordx3 v[23:25], v5, s[4:7], 0 idxen offset:20 ; e03c2014 80011705
buffer_load_dwordx4 v[28:31], v5, s[4:7], 0 idxen offset:48 ; e0382030 80011c05
tbuffer_load_format_xy v[0:1], v5, s[4:7], 0 format:[BUF_FMT_8_8_UNORM] idxen offset:32 ; e8712020 80010005

Foz-DB Navi21:
Totals from 5624 (7.08% of 79395) affected shaders:
MaxWaves: 149894 -> 149898 (+0.00%)
Instrs: 3032697 -> 3034853 (+0.07%); split: -0.05%, +0.12%
CodeSize: 15907852 -> 15915752 (+0.05%); split: -0.05%, +0.10%
VGPRs: 216248 -> 216144 (-0.05%)
Latency: 10955137 -> 11008760 (+0.49%); split: -0.22%, +0.70%
InvThroughput: 2032857 -> 2033916 (+0.05%); split: -0.03%, +0.08%
VClause: 50120 -> 41778 (-16.64%); split: -16.66%, +0.02%
SClause: 62034 -> 62004 (-0.05%); split: -0.33%, +0.29%
Copies: 253836 -> 254505 (+0.26%); split: -0.17%, +0.43%
VALU: 1621606 -> 1622274 (+0.04%); split: -0.03%, +0.07%
SALU: 653251 -> 653252 (+0.00%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34379>
 2025-04-08 09:22:04 +00:00
Georg Lehmann
babe7f3e12 aco/gfx10: simpler solution to avoid store instructions in clauses 
Foz-DB Navi21 has no changes.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34379>
 2025-04-08 09:22:04 +00:00
Samuel Pitoiset
0ba3a8b3cc radv: add clip rects state bit for emitting discard rectangles
Some checks are pending
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Better match the hw naming.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
08918f0880 radv: regroup emitting all MSAA states in one function 
All register writes are optimized out. Also this will allow to use
paired context register writes on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
e8d787e1ef radv: track more MSAA related register writes 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
a327bc677a radv: configure COVERAGE_TO_SHADER_SELECT only if conservative rast is enabled 
When conservative rasterization isn't enabled, FullyCoveredEXT is
expected to return 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
6e9782b39c radv: emit conservative raster mode as part of the MSAA state 
From the hw perspective, it's more like a MSAA state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
ed744b5c68 radv: move emitting raster and depth/stencil state slightly earlier 
To avoid a redundant chekc if no dynamic states are dirtied.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34361>
 2025-04-08 08:42:17 +00:00
Samuel Pitoiset
ef9e7cb3f5 radv: add before/after draw functions for DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
 2025-04-08 08:15:05 +02:00
Samuel Pitoiset
d2da54e6f3 radv: apply the workaround for buggy HiZ/HiS on GFX12 for DGC 
Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
 2025-04-08 08:15:04 +02:00
Samuel Pitoiset
6388db03c8 radv: add a workaround for buggy HiZ/HiS on GFX12 
HiZ/HiS is buggy and can cause random GPU hangs when stencil is enabled.
There are basically two alternatives but RADV follows RadeonSI and emit
a dummy RELEASE_MEM packet after every draw which should workaround the
issue and maintain performance.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12944
Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
 2025-04-08 08:09:13 +02:00
Samuel Pitoiset
11b6d2ba60 radv: determine if HiZ/HiS is enabled earlier on GFX12 
To lower CPU overhead of the hardware workaround.

Backport-to: 25.0
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34381>
 2025-04-08 08:03:11 +02:00
Marek Olšák
e4a30b7241 ac/surface: remove 64K_2D modifier with 64B max compressed blocks for gfx12 
It has no use and is slower.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
 2025-04-07 19:44:22 +00:00
Marek Olšák
27d5be13c6 ac/nir/cull: always do frustum culling, skip only small prim culling 
Only small prim culling uses the viewport state, so only that must be
disabled when there are multiple viewports.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
 2025-04-07 19:44:22 +00:00
Marek Olšák
0f97dc707d ac/nir/cull: rename skip_viewport_culling -> skip_viewport_state_culling 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
 2025-04-07 19:44:22 +00:00
Marek Olšák
bc27ad8064 ac: define physical VGPRs for fake hw overrides 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
 2025-04-07 19:44:22 +00:00
Marek Olšák
1d5c42528b nir/opt_algebraic: lower 16-bit imul_high & umul_high 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34016>
 2025-04-07 19:44:22 +00:00
Samuel Pitoiset
e3c3fa8b9a radv: add a fuction to emit the VRS surface on GFX11
Some checks are pending
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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
00354f0a74 radv: do not emit the VRS surface VA when it's not enabled 
This shouldn't be necessary because VRS_SURFACE_ENABLE is the toggle
bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
9b11caee40 radv: stop emitting CB_FDCC_CONTROL to zero on GFX11-GFX11.5 
It's already emitted by the CLEAR_STATE packet on these GPUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
17e5fd856f radv: split null framebuffer state emission for GFX12 
For consistency with color/ds states emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
c608a601bf radv: split framebuffer depth/stencil state emission for GFX12 
It's also really simpler on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
d5eb1f6833 radv: split framebuffer color state emission for GFX12 
It's really simpler on GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
9dec80d8cf radv: tidy up radv_emit_db_shader_control() 
To separate packet construction and emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
4bc6335e3c radv: restore DB_DFSM_CONTROL properly when POPS isn't used 
It looks safer to restore this register to its initial value when POPS
isn't used. Only VEGA10 and RAVEN are concerned.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
cb390ca234 radv: tidy up radv_emit_raster_state() 
To separate packet construction and emission.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00
Samuel Pitoiset
62e4b1130a radv: remove useless FDCC_ENABLE bitfield clear on GFX12 
This bit doesn't exist.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34357>
 2025-04-07 15:09:18 +00:00