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radv: Add radv_foreach_stage to ForEachMacros again.

Browse source 
This was lost when .clang-format was removed
from the amd folder.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33880>
This commit is contained in:
Timur Kristóf 2025-02-27 14:54:51 +01:00 • committed by Marge Bot
parent 23c0d64e24
commit 412af41258
5 changed files with 21 additions and 37 deletions
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1
src/.clang-format
View file

@ -232,6 +232,7 @@ ForEachMacros:
# radv
- PHASE
- radv_foreach_stage
# Disable clang formatting by default. Drivers that use clang-format
# inherit from this .clang-format file and re-enable formatting:

26
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2911,8 +2911,7 @@ radv_emit_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
radv_foreach_stage(s, cmd_buffer->state.active_stages & RADV_GRAPHICS_STAGE_BITS)
{
radv_foreach_stage (s, cmd_buffer->state.active_stages & RADV_GRAPHICS_STAGE_BITS) {
switch (s) {
case MESA_SHADER_VERTEX:
radv_emit_vertex_shader(cmd_buffer);
@ -5593,8 +5592,7 @@ radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags st
radv_emit_descriptors_per_stage(device, cs, compute_shader, descriptors_state);
} else {
radv_foreach_stage(stage, stages & ~VK_SHADER_STAGE_TASK_BIT_EXT)
{
radv_foreach_stage (stage, stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
if (!cmd_buffer->state.shaders[stage])
continue;
@ -5689,8 +5687,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag
radv_emit_all_inline_push_consts(device, cs, compute_shader, (uint32_t *)cmd_buffer->push_constants,
&need_push_constants);
} else {
radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT)
{
radv_foreach_stage (stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
shader = radv_get_shader(cmd_buffer->state.shaders, stage);
if (!shader)
@ -5728,8 +5725,7 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stag
radv_emit_userdata_address(device, cs, compute_shader, AC_UD_PUSH_CONSTANTS, va);
} else {
prev_shader = NULL;
radv_foreach_stage(stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT)
{
radv_foreach_stage (stage, internal_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
shader = radv_get_shader(cmd_buffer->state.shaders, stage);
/* Avoid redundantly emitting the address for merged stages. */
@ -7782,8 +7778,7 @@ radv_reset_shader_object_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBin
}
break;
case VK_PIPELINE_BIND_POINT_GRAPHICS:
radv_foreach_stage(s, RADV_GRAPHICS_STAGE_BITS)
{
radv_foreach_stage (s, RADV_GRAPHICS_STAGE_BITS) {
if (cmd_buffer->state.shader_objs[s]) {
radv_bind_shader(cmd_buffer, NULL, s);
cmd_buffer->state.shader_objs[s] = NULL;
@ -7858,9 +7853,8 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
return;
radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
radv_foreach_stage(
stage, (cmd_buffer->state.active_stages | graphics_pipeline->active_stages) & RADV_GRAPHICS_STAGE_BITS)
{
radv_foreach_stage (
stage, (cmd_buffer->state.active_stages | graphics_pipeline->active_stages) & RADV_GRAPHICS_STAGE_BITS) {
radv_bind_shader(cmd_buffer, graphics_pipeline->base.shaders[stage], stage);
}
@ -9426,8 +9420,7 @@ radv_emit_view_index_per_stage(struct radeon_cmdbuf *cs, const struct radv_shade
static void
radv_emit_view_index(const struct radv_cmd_state *cmd_state, struct radeon_cmdbuf *cs, unsigned index)
{
radv_foreach_stage(stage, cmd_state->active_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT)
{
radv_foreach_stage (stage, cmd_state->active_stages & ~VK_SHADER_STAGE_TASK_BIT_EXT) {
const struct radv_shader *shader = radv_get_shader(cmd_state->shaders, stage);
radv_emit_view_index_per_stage(cs, shader, shader->info.user_data_0, index);
@ -14173,8 +14166,7 @@ radv_reset_pipeline_state(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoin
break;
case VK_PIPELINE_BIND_POINT_GRAPHICS:
if (cmd_buffer->state.graphics_pipeline) {
radv_foreach_stage(s, cmd_buffer->state.graphics_pipeline->active_stages)
{
radv_foreach_stage (s, cmd_buffer->state.graphics_pipeline->active_stages) {
radv_bind_shader(cmd_buffer, NULL, s);
}
cmd_buffer->state.graphics_pipeline = NULL;

3
src/amd/vulkan/radv_dgc.c
View file

@ -1691,8 +1691,7 @@ dgc_emit_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *seq
nir_builder *b = cs->b;
nir_def *push_constant_stages = dgc_get_push_constant_stages(cs);
radv_foreach_stage(s, stages)
{
radv_foreach_stage (s, stages) {
nir_push_if(b, nir_test_mask(b, push_constant_stages, mesa_to_vk_shader_stage(s)));
{
dgc_emit_push_constant_for_stage(cs, stream_addr, sequence_id, &params, s);

25
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -2064,8 +2064,7 @@ radv_fill_shader_info_ngg(struct radv_device *device, struct radv_shader_stage *
}
struct radv_shader_stage *last_vgt_stage = NULL;
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
if (radv_is_last_vgt_stage(&stages[i])) {
last_vgt_stage = &stages[i];
}
@ -2186,8 +2185,7 @@ radv_fill_shader_info(struct radv_device *device, const enum radv_pipeline_type
const struct radv_graphics_state_key *gfx_state, struct radv_shader_stage *stages,
VkShaderStageFlagBits active_nir_stages)
{
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
bool consider_force_vrs = false;
if (radv_is_last_vgt_stage(&stages[i])) {
@ -2669,8 +2667,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
NIR_PASS(_, mesh, nir_lower_compute_system_values, &o);
}
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
gl_shader_stage next_stage;
if (stages[i].next_stage != MESA_SHADER_NONE) {
@ -2699,8 +2696,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
/* Remove all varyings when the fragment shader is a noop. */
if (noop_fs) {
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
if (radv_is_last_vgt_stage(&stages[i])) {
radv_remove_varyings(stages[i].nir);
break;
@ -2732,8 +2728,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
if (stages[MESA_SHADER_VERTEX].nir && !gfx_state->vs.has_prolog)
NIR_PASS(_, stages[MESA_SHADER_VERTEX].nir, radv_nir_optimize_vs_inputs_to_const, gfx_state);
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
int64_t stage_start = os_time_get_nano();
radv_optimize_nir(stages[i].nir, stages[i].key.optimisations_disabled);
@ -2766,8 +2761,8 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
/* Optimize constant clip/cull distance after linking to operate on scalar io in the last
* pre raster stage.
*/
radv_foreach_stage(i, active_nir_stages & (VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT))
{
radv_foreach_stage (i,
active_nir_stages & (VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)) {
if (stages[i].key.optimisations_disabled)
continue;
@ -2782,8 +2777,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
radv_declare_pipeline_args(device, stages, gfx_state, active_nir_stages);
radv_foreach_stage(i, active_nir_stages)
{
radv_foreach_stage (i, active_nir_stages) {
int64_t stage_start = os_time_get_nano();
radv_postprocess_nir(device, gfx_state, &stages[i]);
@ -3080,8 +3074,7 @@ done:
if (!gfx_pipeline_lib->base.active_stages)
continue;
radv_foreach_stage(s, gfx_pipeline_lib->base.active_stages)
{
radv_foreach_stage (s, gfx_pipeline_lib->base.active_stages) {
creation_feedback->pPipelineStageCreationFeedbacks[num_feedbacks++] = stages[s].feedback;
}
}

3
src/amd/vulkan/radv_shader_object.c
View file

@ -175,8 +175,7 @@ radv_shader_object_init_graphics(struct radv_shader_object *shader_obj, struct r
if (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)
next_stages |= VK_SHADER_STAGE_FRAGMENT_BIT;
radv_foreach_stage(next_stage, next_stages)
{
radv_foreach_stage (next_stage, next_stages) {
struct radv_shader *shaders[MESA_VULKAN_SHADER_STAGES] = {NULL};
struct radv_shader_binary *binaries[MESA_VULKAN_SHADER_STAGES] = {NULL};