Commit graph

61 commits

Author SHA1 Message Date
Marek Olšák
f9fd0c4a55 radeonsi: add support for SQRT
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2015-03-16 12:54:18 +01:00
Marek Olšák
d73c1c1304 radeonsi: add support for FMA
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
2015-03-16 12:54:18 +01:00
Marek Olšák
dfea35666e gallium/radeon: don't use LLVMReadOnlyAttribute for ALU
None of the instructions use a pointer argument.
(+ small cosmetic changes)

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-03-16 12:54:18 +01:00
Marek Olšák
d1d2af2398 radeonsi: use ordered compares for SSG and face selection
Ordered compares are what you have in C. Unordered compares are the result
of negating ordered compares (they return true if either argument is NaN).

That special NaN behavior is completely useless here, and unordered
compares produce horrible code with all stable LLVM versions.
(I think that has been fixed in LLVM git)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-01-07 12:06:43 +01:00
Michel Dänzer
402ab50bed radeon/llvm: Dynamically allocate branch/loop stack arrays
This prevents us from silently overflowing the stack arrays, and allows
arbitrary stack depths.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85454

Cc: mesa-stable@lists.freedesktop.org
Reported-and-Tested-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-10-29 19:01:25 +09:00
Marek Olšák
8067732740 radeonsi: remove shader->input[] and output[] arrays and dependencies
They were reinventing tgsi_shader_info. They are unused now.

radeon_llvm_context::load_input can be NULL if input fetching is implemented
in some other way.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-10-12 23:53:57 +02:00
Tom Stellard
b9f501bc6b radeon/llvm: Use the llvm.rsq.clamped intrinsic for RSQ
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Laurent Carlier <lordheavym@gmail.com>

https://bugs.freedesktop.org/show_bug.cgi?id=80015

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-07-02 14:59:29 -04:00
Michel Dänzer
93b6b1fa83 radeon/llvm: Adapt to AMDGPU.rsq intrinsic change in LLVM 3.5
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2014-06-19 09:58:03 -04:00
Marek Olšák
bd2df40a84 radeon/llvm: add support for non-scalar system values
The sample position is one of them.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
559af1df10 gallium/radeon: fix warnings 2014-02-06 17:43:29 +01:00
Michel Dänzer
404b29d765 radeonsi: Initial geometry shader support
Partly based on the corresponding r600g work by Vadim Girlin and Dave
Airlie.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-01-29 11:06:28 +09:00
Vincent Lejeune
797894036d r600/llvm: Allow arbitrary amount of temps in tgsi to llvm 2013-12-07 18:39:10 +01:00
Aaron Watry
df482fe02f radeon/llvm: fix spelling error
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

CC: "10.0" <mesa-stable@lists.freedesktop.org>
2013-11-15 09:16:49 -08:00
Marek Olšák
900b1863c8 radeon/llvm: fix TGSI_OPCODE_UCMP
This doesn't fix any known issue (I haven't run piglit with this yet),
but the code was obviously completely wrong. It looks like copy-pasted from CMP.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-09-29 14:49:23 +02:00
Marek Olšák
028b26e2ef radeon/llvm: fix shadow cube texturing for GL3.0
The fix is at the end (TGSI_TEXTURE_SHADOWCUBE handling), but I also
restructured the code for it to be more readable.

Fixes spec/!OpenGL 3.0/sampler-cube-shadow.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-09-25 20:45:23 +02:00
Roland Scheidegger
7727fbb7c5 r600/radeonsi: implement new float comparison instructions
Also use ordered comparisons for old cmp instructions.

Tested-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Tom Stellard <tom@stellard.net>
2013-08-15 00:40:14 +02:00
Brian Paul
46205ab8cc tgsi: rename the TGSI fragment kill opcodes
TGSI_OPCODE_KIL and KILP had confusing names.  The former was conditional
kill (if any src component < 0).  The later was unconditional kill.
At one time KILP was supposed to work with NV-style condition
codes/predicates but we never had that in TGSI.

This patch renames both opcodes:
  TGSI_OPCODE_KIL -> KILL_IF   (kill if src.xyzw < 0)
  TGSI_OPCODE_KILP -> KILL     (unconditional kill)

Note: I didn't just transpose the opcode names to help ensure that I
didn't miss updating any code anywhere.

I believe I've updated all the relevant code and comments but I'm
not 100% sure that some drivers had this right in the first place.
For example, the radeon driver might have llvm.AMDGPU.kill and
llvm.AMDGPU.kilp mixed up.  Driver authors should review their code.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-07-12 08:32:51 -06:00
Vinson Lee
36e2c7cc1a radeon: Initialize variables in radeon_llvm_context_init.
'type' was not fully initialized when calling lp_build_context_init.

Fixes "Uninitialized scalar variable" defect reported by Coverity.

NOTE: This is a candidate for the stable branches.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2013-05-22 23:06:23 -07:00
Vincent Lejeune
9fd7ea786c r600g/llvm: fix cubemap lod/bias 2013-05-20 20:23:19 +02:00
José Fonseca
50b3fc6204 gallium: Disambiguate TGSI_OPCODE_IF.
TGSI_OPCODE_IF condition had two possible interpretations:

- src.x != 0.0f

  - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was false either for
    vertex and fragment shaders
  - gallivm/llvmpipe
  - postprocess
  - vl state tracker
  - vega state tracker
  - most old drivers
  - old internal state trackers
  - many graw examples

- src.x != 0U

  - Mesa statetracker when PIPE_SHADER_CAP_INTEGERS was true for both
    vertex and fragment shaders
  - tgsi_exec/softpipe
  - r600
  - radeonsi
  - nv50

And drivers that use draw module also were a mess (because Mesa would
emit float IFs, but draw module supports native integers so it would
interpret IF arg as integers...)

This sort of works if the source argument is limited to float +0.0f or
+1.0f, integer 0, but would fail if source is float -0.0f, or integer in
the float NaN range.  It could also fail if source is integer 1, and
hardware flushes denormalized numbers to zero.

But with this change there are now two opcodes, IF and UIF, with clear
meaning.

Drivers that do not support native integers do not need to worry about
UIF.  However, for backwards compatibility with old state trackers and
examples, it is advisable that native integer capable drivers also
support the float IF opcode.

I tried to implement this for r600 and radeonsi based on the surrounding
code.  I couldn't do this for nouveau, so I just shunted IF/UIF
together, which matches the current behavior.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>

v2:
- Incorporate Roland's feedback.
- Fix r600_shader.c merge conflict.
- Fix typo in radeon, spotted by Michel Dänzer.
- Incorporte  Christoph Bumiller's patch to handle TGSI_OPCODE_IF(float)
  properly in nv50/ir.
2013-04-17 10:54:08 +01:00
Christian König
83df955ca9 radeon/llvm: move system value fetching to common code
This should be used by both SI and R600.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-04-02 13:01:42 +02:00
Christian König
c05483fc00 radeon/llvm: rework input fetch and output store
Cleanup the code and implement indirect addressing.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-03-19 15:16:18 +01:00
Christian König
a7a899584c radeon/llvm: enable LICM and DCE pass v2
LICM stands for Loop Invariant Code Motion. Instructions that
does not depend of loop index are moved outside of loop body.

DCE is DeadCodeElimination.

v2: updated commit msg, thx to Vincent.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-03-07 10:03:22 +01:00
Christian König
55fe5ccb39 radeon/llvm: make SGPRs proper function arguments v2
v2: remove unrelated changes

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-03-07 10:03:22 +01:00
Christian König
886c5085e3 radeon/llvm: fix trivial warnings
Signed-off-by: Christian König <christian.koenig@amd.com>
2013-03-06 12:08:54 +01:00
Michel Dänzer
f6b40ddd2d radeon/llvm: Remove stale comment about radeon_llvm_emit_prepare_cube_coords 2013-02-22 13:06:07 +01:00
Vincent Lejeune
ef8fde6acb r600g/llvm: Add support for UBO
NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
2013-02-18 15:08:45 +01:00
Michel Dänzer
e5fb7347a7 radeonsi: Adapt to sample intrinsics changes.
Fix up intrinsic names, and bitcast texture address parameters to integers.

NOTE: This is a candidate for the 9.1 branch.
2013-02-04 17:03:25 +01:00
Michel Dänzer
a56dfd99e2 radeon/llvm: Handle LP_CHAN_ALL in emit_fetch_immediate().
Fixes piglit spec/ARB_sampler_objects/sampler-incomplete and
spec/EXT_texture_swizzle/depth_texture_mode_and_swizzle.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2013-01-22 18:50:02 +01:00
Vincent Lejeune
ce34ff1ad7 r600g/llvm:translate ARL opcode to a simple cast
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-01-18 20:08:10 +00:00
Vadim Girlin
7d532800d8 r600g/llvm: rework handling of the constants
Vincent Lejeune:
  - tgsi to llvm now emits pointers for constants

Tom Stellard:
  - Only use texture cache for vtx fetch with compute shaders
  - Change address space used for constant loads to match LLVM
    backend.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2013-01-18 20:08:10 +00:00
Vadim Girlin
8cf552b182 radeon/llvm: improve cube map handling
Add support for TEX2, TXB2, TXL2, fix SHADOWCUBE

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-18 17:40:57 +04:00
Vadim Girlin
3b89fcbe54 radeon/llvm: fix TXQ_LZ handling for cube maps
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-12-18 17:40:57 +04:00
Michel Dänzer
aac2154729 radeon/llvm: Export prepare_cube_coords helper to driver.
To be used by radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-06 20:18:40 +01:00
Vincent Lejeune
00d77e9fe4 r600g: use default action for min/max opcode in tgsi to llvm
Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
2012-12-05 18:31:55 +01:00
Vincent Lejeune
2a03f28e54 r600g: use default action for fdiv/rcp opcode
Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
2012-12-05 18:31:02 +01:00
Vincent Lejeune
0ad1fefd69 r600g: Use default mul/mad function for tgsi-to-llvm
Reveiwed-by: Tom Stellard <thomas.stellard at amd.com>
2012-12-05 18:30:16 +01:00
Tom Stellard
8030cb0ed4 radeon/llvm: Sort tgsi opcode action initialization
This was done in order to identify and remove duplicate entries.
2012-10-19 21:25:01 +00:00
Tom Stellard
bd8af8a3dc radeon/llvm: Fix lowering TGSI_OPCODE_SSG 2012-10-19 21:25:00 +00:00
Vincent Lejeune
5090ce42e4 radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-10 22:03:33 +02:00
Vincent Lejeune
9a6bb3f645 radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floor
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-10 22:03:20 +02:00
Vincent Lejeune
bfdf26892c radeon/llvm: use llvm fabs intrinsic
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-10 22:03:03 +02:00
Vincent Lejeune
8db11bc4ed radeon/llvm: use llvm intrinsic for flog2
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-10 22:02:45 +02:00
Vincent Lejeune
23e11ac835 radeon/llvm: add support for cos/sin intrinsic
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-10-10 22:02:28 +02:00
Tom Stellard
87decd6e66 radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version 2012-09-21 19:30:53 +00:00
Christian König
4444b9d1ec radeon/llvm: add support to fetch temps as vectors
Necessary for texture fetches with temp regs as source on SI.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-15 22:13:19 +02:00
Tom Stellard
f92873be2c radeon/llvm: Don't use lp_build_swizzle_aos() for swizzles
This function assumes that lp_build_context::type is a vector type,
which is not true for r600 or radeonsi.

This fixes an assertion failure using glamor 2D accel.
2012-07-12 13:53:22 -04:00
Tom Stellard
cee23ab246 radeon/llvm: Handle selectcc DAG node
R600 can now select instructions from the selectcc DAG node, which is
typically lowered to one of the SET* instructions.
2012-05-20 16:27:31 -04:00
Vadim Girlin
4a8d47c264 radeon/llvm: add support for texture offsets, fix TEX_LD
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:53:20 +04:00
Vadim Girlin
fa5a963dd6 radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-05-15 18:53:06 +04:00