fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 13:00:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions

radeon/llvm: add support for texture offsets, fix TEX_LD

Browse source 
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Vadim Girlin 2012-05-15 18:48:51 +04:00
parent fa5a963dd6
commit 4a8d47c264
4 changed files with 51 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/radeon/AMDGPUIntrinsics.td
View file

@ -42,7 +42,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;

15
src/gallium/drivers/radeon/R600CodeEmitter.cpp
View file

@ -456,9 +456,11 @@ void R600CodeEmitter::emitALU(MachineInstr &MI, unsigned numSrc)
void R600CodeEmitter::emitTexInstr(MachineInstr &MI)
{
int64_t sampler = MI.getOperand(2).getImm();
int64_t textureType = MI.getOperand(3).getImm();
unsigned opcode = MI.getOpcode();
bool hasOffsets = (opcode == AMDIL::TEX_LD);
unsigned op_offset = hasOffsets ? 3 : 0;
int64_t sampler = MI.getOperand(op_offset+2).getImm();
int64_t textureType = MI.getOperand(op_offset+3).getImm();
unsigned srcSelect[4] = {0, 1, 2, 3};
// Emit instruction type
@ -518,10 +520,11 @@ void R600CodeEmitter::emitTexInstr(MachineInstr &MI)
}
// XXX: Emit offsets
emitByte(0); // X
emitByte(0); // Y
emitByte(0); // Z
// There is no OFFSET_W
if (hasOffsets)
for (unsigned i = 2; i < 5; i++)
emitByte(MI.getOperand(i).getImm()<<1);
else
emitNullBytes(3);
// Emit sampler id
emitByte(sampler);

7
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -430,8 +430,11 @@ def CNDE_INT : R600_3OP <
def TEX_LD : R600_TEX <
0x03, "TEX_LD",
[(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2))]
>;
[(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$src4, imm:$src5))]
> {
let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5);
}
def TEX_GET_TEXTURE_RESINFO : R600_TEX <
0x04, "TEX_GET_TEXTURE_RESINFO",

37
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
View file

@ -581,6 +581,7 @@ static void txd_fetch_args(
emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
}
static void txp_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
@ -643,6 +644,40 @@ static void tex_fetch_args(
}
}
static void txf_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
{
const struct tgsi_full_instruction * inst = emit_data->inst;
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
const struct tgsi_texture_offset * off = inst->TexOffsets;
LLVMTypeRef offset_type = bld_base->int_bld.elem_type;
/* fetch tex coords */
tex_fetch_args(bld_base, emit_data);
/* fetch tex offsets */
if (inst->Texture.NumOffsets) {
assert(inst->Texture.NumOffsets == 1);
emit_data->args[1] = LLVMConstBitCast(
bld->immediates[off->Index][off->SwizzleX],
offset_type);
emit_data->args[2] = LLVMConstBitCast(
bld->immediates[off->Index][off->SwizzleY],
offset_type);
emit_data->args[3] = LLVMConstBitCast(
bld->immediates[off->Index][off->SwizzleZ],
offset_type);
} else {
emit_data->args[1] = bld_base->int_bld.zero;
emit_data->args[2] = bld_base->int_bld.zero;
emit_data->args[3] = bld_base->int_bld.zero;
}
emit_data->arg_count = 4;
}
static void emit_icmp(
const struct lp_build_tgsi_action * action,
struct lp_build_tgsi_context * bld_base,
@ -1029,7 +1064,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
bld_base->op_actions[TGSI_OPCODE_UMIN].intr_name = "llvm.AMDGPU.umin";
bld_base->op_actions[TGSI_OPCODE_UMAX].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_UMAX].intr_name = "llvm.AMDGPU.umax";
bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXF].fetch_args = txf_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";