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Author SHA1 Message Date
Rhys Perry
75d9a4a6ce aco: always update orig_names in get_reg_phi() 
No idea why this wasn't done if pc.first was a renamed temporary.

Fixes navi10 RA validation error with
dEQP-VK.binding_model.descriptor_buffer.multiple.graphics_geom_buffers1_sets3_imm_samplers

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8349
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21501>
 2023-02-27 15:10:22 +00:00
Eric Engestrom
735df516e9 radv: split linker script for android since it requires different symbols 
Fixes: 4956f6d0bf ("radv: Add Android module info to linker script.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8338
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21518>
 2023-02-27 14:34:16 +00:00
Mike Blumenkrantz
7c8a5f6e37 vulkan/wsi: switch to using an options struct for last param 
this makes adding values easier since the drivers won't need to be updated

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21447>
 2023-02-27 13:21:21 +00:00
Georg Lehmann
1c5c2f77c3 aco: use and swizzle mask in dpp quad perm 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
8fabde3be4 aco/gfx11: use dpp_row_xmask and dpp_row_share 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
b7cd0eb439 aco: use v_permlane(x)16_b32 for masked swizzle 
Should be cheaper than ds_swizzle.

Totals from 8 (0.01% of 134913) affected shaders:
CodeSize: 16316 -> 16388 (+0.44%)
Instrs: 3088 -> 3086 (-0.06%)
Latency: 49558 -> 49508 (-0.10%)
InvThroughput: 9180 -> 9198 (+0.20%)
Copies: 376 -> 384 (+2.13%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21412>
 2023-02-27 11:09:42 +00:00
Georg Lehmann
9f155c21c3 amd: d16 uses rtz conversion for 32bit float 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Georg Lehmann
77252687fa amd: don't use d16 for integer loads 
D16 saturates to min/max instead of just truncating.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Georg Lehmann
a00b50d820 nir: change 16bit image dest folding option to per type 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21404>
 2023-02-27 09:55:34 +00:00
Samuel Pitoiset
a14d46fde2 radv: enable primitiveUnderestimation on GFX9+ 
It's passing dEQP-VK.rasterization.conservative.underestimate.* on
NAVI21.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
dba7a66429 radv: set MSAA_NUM_SAMPLES to 0 for underestimate rasterization 
Based on PAL.

Fixes
dEQP-VK.rasterization.conservative.underestimate.samples_*.triangles.normal.test.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
0eae617826 radv: stop setting ENABLE_POSTZ_OVERRASTERIZATION to 1 
According to PAL this isn't set.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Samuel Pitoiset
05732f4519 radv: cleanup radv_emit_{conservative,msaa}_state() functions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21459>
 2023-02-27 09:04:01 +00:00
Tatsuyuki Ishi
ed03821442 radv/sqtt: Use code buffer from radv_shader directly instead of copying. 
The reference-counted radv_shader always outlives the pipeline, so we can
use this buffer directly when dumping code objects to the trace.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>
 2023-02-27 07:16:48 +00:00
Tatsuyuki Ishi
ea070fb83a radv: Keep shader code ptr in a separately allocated buffer. 
RGP traces need a dump of shader code in order to display ISA and
instruction trace. Previously, this was read back from GPU at trace
creation time. However, for future changes that implements upload shader
to invisible VRAM, the upload destination will be a temporary staging
buffer and will be only accessible during shader creation.

To allow dumping in such cases, copy the shader code to a separate buffer
at creation time, if thread tracing is enabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21513>
 2023-02-27 07:16:48 +00:00
Qiang Yu
822e756511 ac/llvm,radeonsi: lower fbfetch in abi 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>
 2023-02-27 09:43:53 +08:00
Qiang Yu
5c44404b5f ac/llvm,radeonsi: lower nir_load_barycentric_at_sample in abi 
RADV already did this in radv_lower_fs_intrinsics().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21436>
 2023-02-27 09:39:41 +08:00
Konstantin Seurer
2d93ab795b radv/rt: Pre shift cull_mask 
This removes the need for masking the instance mask.

Totals from 14 (14.43% of 97) affected shaders:
CodeSize: 378696 -> 378308 (-0.10%); split: -0.12%, +0.02%
Instrs: 70854 -> 70855 (+0.00%); split: -0.02%, +0.02%
Latency: 1651235 -> 1651215 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 336290 -> 336285 (-0.00%); split: -0.00%, +0.00%
Copies: 9915 -> 9923 (+0.08%); split: -0.03%, +0.11%
PreSGPRs: 890 -> 896 (+0.67%)

 PERCENTAGE DELTAS Shaders  CodeSize   Instrs   Latency  InvThroughput   Copies   PreSGPRs
 q2rtx-pipe        48        -0.02%    -0.02%    -0.00%      -0.00%      -0.03%      .
 q2rtx_1           49        -0.10%    +0.02%    +0.00%      +0.00%      +0.14%    +0.31%
 -------------------------------------------------------------------------------------------
 All affected      14        -0.10%    +0.00%    -0.00%      -0.00%      +0.08%    +0.67%
 -------------------------------------------------------------------------------------------
 Total             97        -0.06%    +0.00%    -0.00%      -0.00%      +0.06%    +0.16%

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21530>
 2023-02-26 12:58:13 +00:00
Konstantin Seurer
13a9ce7f2f radv/rt: Merge cull_mask and flags 
Since cull_mask is only one byte, we can trivially store it in the same
register as the flags. This leaves us with a 2% performance gain in
Quake II RTX:

Totals from 7 (14.00% of 50) affected shaders:
VGPRs: 720 -> 688 (-4.44%)
CodeSize: 213052 -> 212980 (-0.03%); split: -0.05%, +0.02%
MaxWaves: 67 -> 70 (+4.48%)
Instrs: 39429 -> 39394 (-0.09%); split: -0.15%, +0.06%
Latency: 1096258 -> 1096943 (+0.06%); split: -0.05%, +0.11%
InvThroughput: 230661 -> 222963 (-3.34%); split: -3.42%, +0.08%
VClause: 1208 -> 1206 (-0.17%); split: -0.25%, +0.08%
Copies: 5321 -> 5269 (-0.98%); split: -1.22%, +0.24%
Branches: 1903 -> 1902 (-0.05%)
PreVGPRs: 650 -> 645 (-0.77%)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>
 2023-02-25 12:07:46 +00:00
Marek Olšák
9f1e6d8f70 nir,amd: add and use nir_intrinsic_load_esgs_vertex_stride_amd 
This will emulate VGT_ESGS_RING_ITEMSIZE, which does the multiplication
for us. It's beneficial to stop setting VGT_ESGS_RING_ITEMSIZE to reduce
context rolls, and also the register will be removed in the future.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
5e837f9594 amd/gpu_info: add a workaround for SI_FORCE_FAMILY=gfx1100 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
df6380ddc9 amd: implement conformant TRUNC_COORD behavior for gfx11 
For testing, the conformant behavior can be enabled by setting
conformant_trunc_coord to true manually and running this to enable
the conformant behavior in hw:
    umr -w *.*.regTA_CNTL2 0x40000

The layer index rounding and TRUNC_COORD resetting workarounds can disabled
in the shader compiler.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
3e8bd05020 radeonsi: don't set PACKET_TO_ONE_PA for line stippling 
A hw guy told me this.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
be8c61b4f6 amd/registers: only define SPI and COMPUTE registers in the 0xB000 range 
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
80c0efa50f amd: query the per-SIMD VGPR counts from the kernel, don't hardcode them 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
98eee7dee3 amd: replace SI_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIAN 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
e0c8b24e22 amd/registers: unify VRS combiner definition names between gfx103 and gfx11 
use gfx11 names

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
091268944d amd,radeonsi: remove unused LLVM functions 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:24 +00:00
Marek Olšák
34c01cf718 amd: bump AMD_MAX_SE and change the CU mask type to 16 bits 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:23 +00:00
Marek Olšák
63b21e3066 amd: add missing gfx11 register definitions 
Fixes: caa09f66ae - amd: add chip identification for gfx1100-1103

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:23 +00:00
Marek Olšák
ac0e83375a amd: fix LOD_BIAS on gfx6-9 and adjust the lod bias CAP 
Fixes: e673bb4ae4 - amd,util: fix how lod bias is converted to fixed-point

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:23 +00:00
Marek Olšák
fb70d8cf9c Revert "radeonsi/ci: Update stoney test expectations" 
This reverts commit 53cc509288.

This MR fixes it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21525>
 2023-02-24 21:27:23 +00:00
Faith Ekstrand
96c832c47e spirv: Always emit deref_buffer_array_length intrinsics 
All the drivers have been converted to setting this option now except
imagination and they don't support SSBOs yet.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3993
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21446>
 2023-02-24 20:37:10 +00:00
Konstantin Seurer
e2fa9ba9c6 radv: Use indirect header filling for compact builds 
Sets the accel struct size fields to the correct values which should
allow for more compaction.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
40e9efa2de radv/bvh: Add a shader for filling the header 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
c83ea20683 radv/bvh: Move the size header field up 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
b0fd43f1f7 radv: Move the geometry infos before the BVH 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
0800450cb9 radv: Use compact encoding 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
07c1b23022 radv/bvh: Implement compact encoding 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
71ccc8d600 radv: Add a build config for compact builds 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
da4f498f6f radv/bvh/encoder: Move dst_node initialization into the loop 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
2792d012d2 radv/bvh/encode: Introduce is_root_node 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
2c0e158ae2 radv/bvh/encode: Move bvh_offset NULL check to the top of the loop 
NULL nodes don't have to be encoded and they also don't carry over any
information to their children.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
4e87a01b93 radv/bvh: Replace is_final_tree with bvh_offset 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Konstantin Seurer
688f598237 radv/bvh/encode: Use the node type for identifying internal nodes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20818>
 2023-02-24 15:14:40 +00:00
Samuel Pitoiset
d2ff8b673a radv: advertise VK_EXT_image_sliced_view_of_3d on GFX10+ 
Pass dEQP-VK.pipeline.monolithic.sliced_view_of_3d_image.* on NAVI21.

Looks like older generations can't support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>
 2023-02-24 14:12:22 +00:00
Samuel Pitoiset
5520a40e05 radv: implement VK_EXT_image_sliced_view_of_3d on GFX10+ 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>
 2023-02-24 14:12:22 +00:00
Samuel Pitoiset
e82c11df66 ac/nir: add resinfo lowering for sliced storage 3D views 
The first layer isn't necessarily 0 and depth shouldn't be minified.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21359>
 2023-02-24 14:12:22 +00:00
Bas Nieuwenhuizen
ed76833705 radv: Implement & expose VK_EXT_pipeline_library_group_handles. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00
Bas Nieuwenhuizen
d0f7587109 radv: Use group handles based on shader hashes. 
Should be stable.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21406>
 2023-02-23 22:17:30 +00:00