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radv/rt: Merge cull_mask and flags
Since cull_mask is only one byte, we can trivially store it in the same register as the flags. This leaves us with a 2% performance gain in Quake II RTX: Totals from 7 (14.00% of 50) affected shaders: VGPRs: 720 -> 688 (-4.44%) CodeSize: 213052 -> 212980 (-0.03%); split: -0.05%, +0.02% MaxWaves: 67 -> 70 (+4.48%) Instrs: 39429 -> 39394 (-0.09%); split: -0.15%, +0.06% Latency: 1096258 -> 1096943 (+0.06%); split: -0.05%, +0.11% InvThroughput: 230661 -> 222963 (-3.34%); split: -3.42%, +0.08% VClause: 1208 -> 1206 (-0.17%); split: -0.25%, +0.08% Copies: 5321 -> 5269 (-0.98%); split: -1.22%, +0.24% Branches: 1903 -> 1902 (-0.05%) PreVGPRs: 650 -> 645 (-0.77%) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21470>
This commit is contained in:
Konstantin Seurer
Marge Bot
parent
8ae5a42990
commit
13a9ce7f2f
1 changed files with 21 additions and 17 deletions
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@ -103,8 +103,7 @@ struct rt_variables {
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/* trace_ray arguments */
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nir_variable *accel_struct;
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nir_variable *flags;
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nir_variable *cull_mask;
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nir_variable *cull_mask_and_flags;
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nir_variable *sbt_offset;
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nir_variable *sbt_stride;
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nir_variable *miss_index;
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@ -167,8 +166,8 @@ create_rt_variables(nir_shader *shader, const VkRayTracingPipelineCreateInfoKHR
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const struct glsl_type *vec3_type = glsl_vector_type(GLSL_TYPE_FLOAT, 3);
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vars.accel_struct =
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nir_variable_create(shader, nir_var_shader_temp, glsl_uint64_t_type(), "accel_struct");
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vars.flags = nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "ray_flags");
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vars.cull_mask = nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "cull_mask");
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vars.cull_mask_and_flags =
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nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "cull_mask_and_flags");
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vars.sbt_offset =
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nir_variable_create(shader, nir_var_shader_temp, glsl_uint_type(), "sbt_offset");
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vars.sbt_stride =
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@ -215,8 +214,7 @@ map_rt_variables(struct hash_table *var_remap, struct rt_variables *src,
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_mesa_hash_table_insert(var_remap, src->launch_id, dst->launch_id);
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_mesa_hash_table_insert(var_remap, src->accel_struct, dst->accel_struct);
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_mesa_hash_table_insert(var_remap, src->flags, dst->flags);
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_mesa_hash_table_insert(var_remap, src->cull_mask, dst->cull_mask);
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_mesa_hash_table_insert(var_remap, src->cull_mask_and_flags, dst->cull_mask_and_flags);
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_mesa_hash_table_insert(var_remap, src->sbt_offset, dst->sbt_offset);
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_mesa_hash_table_insert(var_remap, src->sbt_stride, dst->sbt_stride);
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_mesa_hash_table_insert(var_remap, src->miss_index, dst->miss_index);
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@ -377,9 +375,10 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
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/* Per the SPIR-V extension spec we have to ignore some bits for some arguments. */
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nir_store_var(&b_shader, vars->accel_struct, intr->src[0].ssa, 0x1);
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nir_store_var(&b_shader, vars->flags, intr->src[1].ssa, 0x1);
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nir_store_var(&b_shader, vars->cull_mask,
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nir_iand_imm(&b_shader, intr->src[2].ssa, 0xff), 0x1);
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nir_store_var(&b_shader, vars->cull_mask_and_flags,
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nir_ior(&b_shader, nir_iand_imm(&b_shader, intr->src[2].ssa, 0xff),
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nir_ishl_imm(&b_shader, intr->src[1].ssa, 8)),
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0x1);
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nir_store_var(&b_shader, vars->sbt_offset,
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nir_iand_imm(&b_shader, intr->src[3].ssa, 0xf), 0x1);
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nir_store_var(&b_shader, vars->sbt_stride,
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@ -481,7 +480,7 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
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break;
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}
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case nir_intrinsic_load_ray_flags: {
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ret = nir_load_var(&b_shader, vars->flags);
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ret = nir_ishr_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), 8);
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break;
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}
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case nir_intrinsic_load_ray_hit_kind: {
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@ -536,7 +535,8 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
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break;
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}
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case nir_intrinsic_load_cull_mask: {
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ret = nir_load_var(&b_shader, vars->cull_mask);
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ret =
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nir_iand_imm(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags), 0xff);
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break;
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}
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case nir_intrinsic_ignore_ray_intersection: {
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@ -585,6 +585,10 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
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ret = nir_load_var(&b_shader, vars->accel_struct);
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break;
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}
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case nir_intrinsic_load_cull_mask_and_flags_amd: {
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ret = nir_load_var(&b_shader, vars->cull_mask_and_flags);
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break;
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}
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case nir_intrinsic_execute_closest_hit_amd: {
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nir_store_var(&b_shader, vars->tmax, intr->src[1].ssa, 0x1);
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nir_store_var(&b_shader, vars->primitive_id, intr->src[2].ssa, 0x1);
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@ -594,8 +598,8 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
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load_sbt_entry(&b_shader, vars, intr->src[0].ssa, SBT_HIT, SBT_CLOSEST_HIT_IDX);
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nir_ssa_def *should_return =
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nir_test_mask(&b_shader, nir_load_var(&b_shader, vars->flags),
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SpvRayFlagsSkipClosestHitShaderKHRMask);
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nir_test_mask(&b_shader, nir_load_var(&b_shader, vars->cull_mask_and_flags),
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SpvRayFlagsSkipClosestHitShaderKHRMask << 8);
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if (!(vars->create_info->flags &
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VK_PIPELINE_CREATE_RAY_TRACING_NO_NULL_CLOSEST_HIT_SHADERS_BIT_KHR)) {
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@ -1337,8 +1341,8 @@ build_traversal_shader(struct radv_device *device,
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/* initialize trace_ray arguments */
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nir_ssa_def *accel_struct = nir_load_accel_struct_amd(&b);
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nir_store_var(&b, vars.flags, nir_load_ray_flags(&b), 0x1);
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nir_store_var(&b, vars.cull_mask, nir_load_cull_mask(&b), 0x1);
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nir_ssa_def *cull_mask_and_flags = nir_load_cull_mask_and_flags_amd(&b);
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nir_store_var(&b, vars.cull_mask_and_flags, cull_mask_and_flags, 0x1);
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nir_store_var(&b, vars.sbt_offset, nir_load_sbt_offset_amd(&b), 0x1);
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nir_store_var(&b, vars.sbt_stride, nir_load_sbt_stride_amd(&b), 0x1);
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nir_store_var(&b, vars.origin, nir_load_ray_world_origin(&b), 0x7);
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@ -1410,8 +1414,8 @@ build_traversal_shader(struct radv_device *device,
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struct radv_ray_traversal_args args = {
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.root_bvh_base = root_bvh_base,
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.flags = nir_load_var(&b, vars.flags),
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.cull_mask = nir_load_var(&b, vars.cull_mask),
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.flags = nir_ishr_imm(&b, cull_mask_and_flags, 8),
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.cull_mask = cull_mask_and_flags,
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.origin = nir_load_var(&b, vars.origin),
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.tmin = nir_load_var(&b, vars.tmin),
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.dir = nir_load_var(&b, vars.direction),
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