0886be09 ("glsl: Allow precision mismatch on dead data with GLSL ES 1.00")
allowed precision mismatches on uniforms, however if you lower precision on
16-bit consts, then this error triggers instead.
So here we relax the type matching and just make sure we match int vs
float.
Fixes: 0886be09 ("glsl: Allow precision mismatch on dead data with GLSL ES 1.00")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5337
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40107>
In particular, sharable shaders can be used from multiple threads/ctxs,
making the non-atomic refcnting unsound.
But we can avoid making the refcnting atomic just for this one specific
case by passing a flag to indicate whether the stateobj should be un-
reffed.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40177>
This makes use of VK_KHR_pipeline_executable_properties and
VK_EXT_subgroup_size_control to query supported subgroup sizes and to
query which one the driver picks for a given pipeline.
This fixes OpenCL subgroups on drivers with multiple supported subgroup
sizes.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37169>
This might introduce some flakiness due to the inherent "only one process
can have HyperZ lock" feature. So it might not catch regressions reliably,
but probably better than no coverage at all.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39914>
AMD docs support this:
R5xx Acceleration v1.5 says safest handling for ZFUNC changes is to disable
HiZ except specific LESS/LEQUAL and GREATER/GEQUAL transitions.
ATI OpenGL Programming and Optimization Guide advises avoiding ALWAYS when
trying to benefit from HiZ so that would imply fglrx also disables HiZ
there.
On RV530 this fixes the following dEQPs:
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.43
dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.74
Fixes: 12dcbd5954 ("r300g: enable Hyper-Z by default on r500")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8093
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39914>
The DISCARD_WHOLE_RESOURCE path in vc4_map_usage_prep() replaces the
resource's BO with vc4_resource_bo_alloc(). As the RCL resolves
rsc->bo at job submit in vc4_submit_setup_rcl_surface(), any pending
write job would store to the new BO instead of the old one, corrupting
the new written data.
This is the same bug that was fixed in v3d in the previous commit.
Fixes: 18ccda7b86 ("vc4: When asked to discard-map a whole resource, discard it.")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40180>
The DISCARD_WHOLE_RESOURCE path in v3d_map_usage_prep() replaces the
resource's BO with v3d_resource_bo_alloc(). As the RCL resolves
rsc->bo at job submit in emit_rcl() any pending write job would
store to the new BO instead of the old one, corrupting the new
written data.
This is adressed by flushing all pending write jobs affecting the
resource before replacing its BO.
This fixes multiple tests where data copied to a renderbuffer was
overwritten by a previos GPU clear. Test are from the subgroup:
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.*
Fixes: 45bb8f2957 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40180>
We currently use a custom kernel in blu/linux to run the ci for svga,
instead switch to the kernel used by other drivers.
Signed-off-by: Maaz Mombasawala <maaz.mombasawala@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40016>
Without this libva won't be able to find the driver without
LIBVA_DRIVER_NAME trickery, because the driver has a generic name.
But in the DRI case, even LIBVA_DRIVER_NAME won't do, because the driver
name needs to end with "_drv_video.so", which it doesn't.
So let's instead set up symlinks in the build-dir, like DRIL does.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40136>
We're setting this in the non-DRI codepath, but this was missed when we
started embedding the VA driver into libgallium. This means we no longer
were able to use VA-API from meson devenv, like we could before.
Fixes: 212d57f7e6 ("targets/va: Build va driver into libgallium when building with dri")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40136>
This change is useful when the compute shader is called multiple
times with the atomic operations enabled. It fixes some data
coherency issues. This is done by moving
evergreen_emit_atomic_buffer_setup() after r600_flush_emit().
This change is also a partial fix for compute_shader.pipeline-compute-chain.
In this specific case, it makes the memory barrier working.
This change was tested on cayman and barts; it makes these tests
fully deterministic:
khr-gl4[2-6]/shader_atomic_counters/advanced-usage-many-dispatches: fail pass
khr-gles31/core/shader_atomic_counters/advanced-usage-many-dispatches: fail pass
deqp-gles31/functional/synchronization/inter_call/without_memory_barrier/atomic_counter_dispatch_.*_calls_.*_invocations: fail pass
Cc: mesa-stable
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40037>
The alpha instruction always wrote to the same rendertarget as the rgb and the
original target was ignored (surprisingly the HW docs explicitly allows rgb and
alpha to write to different targets). This makes tesseract rendering a bit
better, but there are still some remaining issues.
Fixes: 1c2c4ddbd1 ("r300g: copy the compiler from r300c")
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40128>
When building with "-Dvideo-codecs=h264dec,h265dec,av1dec" va/encode.c
won't be built but it's still required because it's used from
picture.c
Fixes: c4f05bdf60 ("frontends/va: include picture_*.c based on selected codec")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
On GPUs with ETNA_FEATURE_S8, the hardware supports native 8bpp
stencil buffers. The blob driver samples these as R8I (8-bit integer).
This enables the stencil blit fallback to work with pure S8_UINT
stencil buffers, fixing
dEQP-GLES3.functional.fbo.blit.depth_stencil.stencil_index8_scale
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
Previously, stencil-only blits were silently skipped with "cannot blit
stencil, skipping" because neither the BLT nor RS engines can
selectively copy individual channels from packed depth/stencil formats.
On HALTI5+ GPUs that support stencil texturing (S8X24_UINT), use
util_blitter_stencil_fallback() to perform a shader-based stencil blit.
This clears the destination stencil to zero, then copies each stencil
bit individually using draw calls with per-bit DSA write masks.
Fixes dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
After a BLT blit invalidates the destination's tile status,
ETNA_DIRTY_DERIVE_TS was not set, so etna_update_ts_config() would not
run before the next draw. This caused TS_MEM_CONFIG to retain stale
DEPTH_FAST_CLEAR/DEPTH_COMPRESSION bits from the previous draw, even
though the destination depth data was overwritten by the blit.
This fixes depth/stencil blit tests like
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_basic.
The RS blit path already sets this dirty bit.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
Adds missing FLUSH_CACHE event, and combines the flushing with existing
barrier emit to avoid duplicating flushes.
Fixes some flakeyness seen with UBWC images on gen8.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
Avoid creating a dummy batch in the non-TC (async-flush) path, if we can
re-use last_fence.
This avoids extra flushes with rusticl, which is not using TC.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
When we have a sequence of batches to flush (ie. some batch, and all
it's dependent batches), attach a fence to the last in sequence. This
helps avoid fd_context_flush() from creating an empty batch when it
needs to return a fence, but has nothing else left to flush.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
