fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-16 05:28:14 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
173755 commits 66 branches 935 tags 1 GiB
Commit graph

7449 commits

Author SHA1 Message Date
Joshua Ashton
c9ac960b6a radv: Implement VK_EXT_pipeline_robustness 
Funnel the data from the pNext into the new pipeline key members for buffer robustness

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912>
 2023-07-04 21:04:38 +01:00
Joshua Ashton
3e269c7a4e radv: Rename radv_required_subgroup_info to radv_shader_stage_key 
Additionally, prefix the members that are subgroup related with subgroup_

We will use this structure to store pipeline robustness information.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912>
 2023-07-04 21:04:34 +01:00
Joshua Ashton
2c6125c1c5 radv: Split and move buffer robustness to shader key 
Will be used by pipeline robustness.

There is also loads of space in the first dword.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912>
 2023-07-04 21:04:30 +01:00
Joshua Ashton
3e36b47b96 radv: Rename radv_nir_compiler_options::robust_buffer_access to robust_buffer_access_llvm 
This is only used by LLVM, make that clearer.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912>
 2023-07-04 21:04:21 +01:00
Joshua Ashton
f52ebc8b40 radv: Refactor buffer robustness to an enum 
Will be taken advantage of with pipeline robustness.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912>
 2023-07-04 21:04:10 +01:00
Yonggang Luo
0fbec6dd79 radv: Use nir_remove_non_entrypoints in radv_shader.c 
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23902>
 2023-07-03 21:45:35 +00:00
Konstantin Seurer
20beebb041 amd: Move ac_hw_stage to its own file 
Otherwise ACO has to include ac_shader_util.h which also includes NIR.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23906>
 2023-07-03 21:12:45 +00:00
Connor Abbott
d322a80170 radv: Fix radv_pipeline_is_blend_enabled 
This was relying on cb being NULL instead of just gracefully handling
it, and it will stop being NULL once we start tracking attachment count
as state. Moreover is was broken in the case where only the blend enable
is dynamic.

Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22301>
 2023-07-03 19:51:05 +00:00
Tatsuyuki Ishi
94b92718d9 radv: Enable weak reference cache for device->mem_cache. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23878>
 2023-07-03 17:59:07 +00:00
Daniel Schürmann
3bd72eec1e radv: reference pipeline cache object in radv_pipeline 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23878>
 2023-07-03 17:59:07 +00:00
Konstantin Seurer
1ea963c00b radv: Use nir_builder_at 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23883>
 2023-07-03 15:21:37 +00:00
Rhys Perry
b3b9b22c95 radv: call nir_lower_int64 later 
I would rather this be after several of these complicated lowering passes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23926>
 2023-07-03 10:38:27 +00:00
Rhys Perry
38cff03e58 radv: use nir_lower_conv64 
This has a more accurate i2f/u2f implementation.

fossil-db (navi21):
Totals from 342 (0.26% of 133461) affected shaders:
MaxWaves: 10480 -> 10472 (-0.08%)
Instrs: 273455 -> 274019 (+0.21%); split: -0.02%, +0.22%
CodeSize: 1545020 -> 1546852 (+0.12%); split: -0.11%, +0.23%
VGPRs: 9528 -> 9552 (+0.25%)
SpillSGPRs: 553 -> 592 (+7.05%); split: -2.71%, +9.76%
SpillVGPRs: 821 -> 811 (-1.22%); split: -1.71%, +0.49%
Latency: 3837590 -> 3822989 (-0.38%); split: -0.52%, +0.14%
InvThroughput: 1284512 -> 1277012 (-0.58%); split: -0.77%, +0.19%
VClause: 6480 -> 6486 (+0.09%); split: -0.15%, +0.25%
SClause: 6640 -> 6645 (+0.08%); split: -0.02%, +0.09%
Copies: 45858 -> 46160 (+0.66%); split: -0.10%, +0.76%
Branches: 8736 -> 8741 (+0.06%); split: -0.01%, +0.07%
PreSGPRs: 14320 -> 14323 (+0.02%)
PreVGPRs: 8545 -> 8551 (+0.07%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9275
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23926>
 2023-07-03 10:38:27 +00:00
Timur Kristóf
bd43d9e3d9 radv: Enable required subgroup size on mesh/task. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23925>
 2023-07-03 10:49:11 +02:00
Timur Kristóf
34ace6688a radv: Use required subgroup info for graphics shaders. 
We plan to allow setting this on some graphics shader stages.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23925>
 2023-07-03 10:49:00 +02:00
Timur Kristóf
8982bd6045 radv: Refactor required subgroup size in pipeline key. 
This is to allow setting required subgroup size and
full subgroups on more than just the compute stage.

Use an enum (not the actual subgroup size integer)
so that we can have some bits reserved there for
future use.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23925>
 2023-07-03 10:47:39 +02:00
Samuel Pitoiset
b544a6d6c3 radv: emit PA_SC_SCREEN_SCISSOR_BR with the actual fb extent 
For some reasons, this register is needed for RGP to report actual
render/depth targets size instead of 0 for both width/height. It
doesn't seem to have any other effects.

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9169
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23921>
 2023-06-30 06:38:53 +00:00
Juston Li
33ee59af1d radv: fix incorrect size for primitives generated query 
Primitives generated queries write 1 integer, the primitives-generated
count that is incremented every time a primitive emitted to that stream
reaches the transform feedback stage.

Fixes: 1ebf463a5a ("radv: implement VK_EXT_primitives_generated_query")
Signed-off-by: Juston Li <justonli@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23915>
 2023-06-29 16:58:50 +00:00
Georg Lehmann
130fbda71b radv: set has_bit_test for aco 
Foz-DB Navi21:
Totals from 15285 (11.52% of 132657) affected shaders:
VGPRs: 1019136 -> 1019000 (-0.01%); split: -0.02%, +0.01%
SpillSGPRs: 10889 -> 10909 (+0.18%)
SpillVGPRs: 901 -> 914 (+1.44%); split: -0.89%, +2.33%
CodeSize: 103578640 -> 103523220 (-0.05%); split: -0.08%, +0.03%
MaxWaves: 259782 -> 259820 (+0.01%)
Instrs: 19247383 -> 19223764 (-0.12%); split: -0.15%, +0.02%
Latency: 323877613 -> 323684655 (-0.06%); split: -0.10%, +0.04%
InvThroughput: 62505295 -> 62386541 (-0.19%); split: -0.21%, +0.02%
VClause: 366162 -> 366136 (-0.01%); split: -0.03%, +0.02%
SClause: 786505 -> 785527 (-0.12%); split: -0.22%, +0.10%
Copies: 1348920 -> 1349209 (+0.02%); split: -0.26%, +0.29%
Branches: 456331 -> 456324 (-0.00%); split: -0.01%, +0.00%
PreSGPRs: 849542 -> 849402 (-0.02%); split: -0.02%, +0.01%
PreVGPRs: 925300 -> 924678 (-0.07%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23298>
 2023-06-29 13:39:30 +00:00
Erik Faye-Lund
a6da9d7147 amd: use imm-helpers 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23855>
 2023-06-29 07:08:19 +00:00
Joshua Ashton
68b9ad0ba7 radv: Do not enable robustness for push constants with robustBufferAccess2 
There is no spec text requiring this behaviour, it is only for buffers.

Signed-off-by: Joshua Ashton <joshua@froggi.es>

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23885>
 2023-06-28 20:49:30 +00:00
Konstantin Seurer
1e2f647fbb radv/rt: Hash stages using radv_hash_shaders 
The hash also depends on the radv_pipeline_key as well as the flags. The
pipeline layout will also play a role when we implement inline
descriptor sets and push constants.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Konstantin Seurer
de1092e256 radv/rt: Fix caching non-recursive stages 
The hash used for insertion is calculated in a different way than the
hash used for lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
 2023-06-28 19:45:25 +00:00
Samuel Pitoiset
3f7ea95bc9 radv: inline more values in radv_emit_fb_ds_state() 
These are no longer adjusted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Samuel Pitoiset
5010ab8fff radv: stop emitting TILE_SURFACE_ENABLE for the ZRANGE_PRECISION workaround 
The only case that matters is when the fb is emitted, but HTILE is
already disabled there using DB_RENDER_CONTROL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887>
 2023-06-28 13:21:44 +00:00
Samuel Pitoiset
7b8c6cedcf radv: allow NV_device_generated_commands with RADV_DEBUG=noibs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
277b2afd70 radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs 
This contains some preliminary work to be able to execute DGC cmdbuf
on the compute queue because IB2 doesn't exist.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Samuel Pitoiset
82c60b41e9 radv/amdgpu: add more small helpers for managing CS 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23791>
 2023-06-28 06:34:20 +00:00
Rhys Perry
79d935ceaf radv: use nir_opt_intrinsics 
No fossil-db changes (navi21).

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23621>
 2023-06-27 18:53:50 +00:00
Alyssa Rosenzweig
069cca9d66 treewide: Remove unused builders 
-Wunused-variables kicks in now that it can see through the init.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
173b9ee69a treewide: Use nir_builder_create more 
perl -p0e 's/nir_builder_init\(&([^,]*), /\1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Alyssa Rosenzweig
815efcdf7e nir: Use nir_builder_create 
perl -p0e 's/nir_builder ([^;]*);\s*nir_builder_init\(&\1, /nir_builder \1 = nir_builder_create(/g' -i $(git grep -l nir_builder_init)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23860>
 2023-06-27 18:13:02 +00:00
Konstantin Seurer
17f3f5fa85 amd: Use nir_ instead of nir_build_ helpers 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23858>
 2023-06-27 17:37:54 +00:00
Samuel Pitoiset
9b00867327 radv/amdgpu: workaround a kernel bug when replacing sparse mappings 
AMDGPU has a bug when clearing mappings for BOs that are always valid
in VM with OP_REPLACE.

See https://lists.freedesktop.org/archives/amd-gfx/2023-June/094648.html

The current workaround is to re-use OP_MAP/OP_UNMAP until all stable
kernels have the fix.

This partially reverts "radv/winsys: update sparse mappings with
OP_REPLACE instead of OP_MAP/OP_UNMAP".

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
 2023-06-27 13:13:03 +00:00
Samuel Pitoiset
51caece74c radv/amdgpu: skip adding per VM BOs for sparse during CS BO list build 
This should be similar but it will help for re-introducing
OP_MAP/ON_UNMAP instead of OP_REPLACE.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23741>
 2023-06-27 13:13:03 +00:00
Konstantin Seurer
b0beca8c7a vulkan/rmv,radv: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
e0641ed59f radv/rgp: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
3e11640127 radv/rra: Use common trace trigger 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
15d6618a12 radv: Add radv_trace_mode 
...and add the RADV specific trace modes to the VK instance.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20573>
 2023-06-27 06:25:56 +00:00
Konstantin Seurer
7a7b1a4f71 radv: Call radv_pipeline_init_scratch per shader 
Compute pipelines only have one shader, which was not handled correctly
in the case of ray tracing pipelines. Adding radv_shader as an argument
allows us to handle the ray tracing prolog. The original loop is inlined
into its only user (radv_pipeline_graphics.c).

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23812>
 2023-06-27 06:04:18 +00:00
Vitaliy Triang3l Kuzmin
f9e6d35f65 radv: Enable VK_EXT_fragment_shader_interlock 
ACO only currently - not available in LLVM.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
ec0778f59e radv: Disable VRS forcing with Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
787a553262 radv: Apply the POPS missed overlap hardware bug workaround 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
3831860b20 radv: Handle Primitive Ordered Pixel Shading in DB_SHADER_CONTROL 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
37e325fe15 radv: Enable the null export workaround with POPS 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
7eabc5d6fc radv: Enable POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
50e680d05a radv: Declare POPS collision wave ID shader argument 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
1812819e66 radv: Ensure 1x1 shading rate on GFX10.3 with interlock execution mode 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
08c582ea69 radv: Detect the use of Primitive Ordered Pixel Shading 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00
Vitaliy Triang3l Kuzmin
5449a2c988 radv: Remove unconditional POPS_DRAIN_PS_ON_OVERLAP setting 
This hardware hang workaround (PAL waMiscPopsMissedOverlap) is needed only
on some Vega chips, and only for 8 or more samples per pixel. It has a
significant performance cost (around 1.5x-2x in
nvpro-samples/vk_order_independent_transparency), so it should be precisely
configured when setting up Primitive Ordered Pixel Shading.

It was added in 47b780be21, when POPS was not
used in Mesa, with the change being described as "this may not be needed
yet, but let's set it now".

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
 2023-06-26 15:58:04 +00:00