fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 18:18:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv/rt: Fix caching non-recursive stages

Browse source 
The hash used for insertion is calculated in a different way than the
hash used for lookup.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23747>
This commit is contained in:
Konstantin Seurer 2023-06-20 16:39:41 +02:00 • committed by Marge Bot
parent c9a5cac4ff
commit de1092e256
1 changed files with 1 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -374,11 +374,9 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca
stages[idx].stack_size = stack_size;
stages[idx].shader = shader ? &shader->base : NULL;
} else {
uint8_t shader_sha1[SHA1_DIGEST_LENGTH];
radv_hash_shaders(shader_sha1, &stage, 1, NULL, key, radv_get_hash_flags(device, false));
stages[idx].stack_size = stage.nir->scratch_size;
stages[idx].shader =
radv_pipeline_cache_nir_to_handle(device, cache, stage.nir, shader_sha1, !key->optimisations_disabled);
radv_pipeline_cache_nir_to_handle(device, cache, stage.nir, stages[idx].sha1, !key->optimisations_disabled);
}
ralloc_free(stage.nir);