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radv: Ensure 1x1 shading rate on GFX10.3 with interlock execution mode

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22250>
This commit is contained in:
Vitaliy Triang3l Kuzmin 2023-06-03 00:29:31 +03:00 • committed by Marge Bot
parent 08c582ea69
commit 1812819e66
3 changed files with 18 additions and 6 deletions
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10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2254,8 +2254,7 @@ radv_should_force_vrs1x1(struct radv_cmd_buffer *cmd_buffer)
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
return pdevice->rad_info.gfx_level >= GFX10_3 &&
(cmd_buffer->state.ms.sample_shading_enable ||
(ps && ps->info.ps.reads_sample_mask_in && !ps->info.ps.needs_poly_line_smooth));
(cmd_buffer->state.ms.sample_shading_enable || (ps && ps->info.ps.force_sample_iter_shading_rate));
}
static void
@ -2314,8 +2313,7 @@ radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)
/* Disable VRS and use the rates from PS_ITER_SAMPLES if:
*
* 1) sample shading is enabled or per-sample interpolation is used by the fragment shader
* 2) the fragment shader reads gl_SampleMaskIn because the 16-bit sample coverage mask isn't
* enough for MSAA8x and 2x2 coarse shading isn't enough.
* 2) the fragment shader requires 1x1 shading rate for some other reason
*/
if (radv_should_force_vrs1x1(cmd_buffer)) {
pa_cl_vrs_cntl |= S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE);
@ -6339,8 +6337,8 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (!previous_ps || previous_ps->info.ps.reads_fully_covered != ps->info.ps.reads_fully_covered)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CONSERVATIVE_RAST_MODE;
if (gfx_level >= GFX10_3 &&
(!previous_ps || previous_ps->info.ps.reads_sample_mask_in != ps->info.ps.reads_sample_mask_in))
if (gfx_level >= GFX10_3 && (!previous_ps || previous_ps->info.ps.force_sample_iter_shading_rate !=
ps->info.ps.force_sample_iter_shading_rate))
cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES | RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;

1
src/amd/vulkan/radv_shader.h
View file

@ -384,6 +384,7 @@ struct radv_shader_info {
uint8_t color0_written;
bool load_provoking_vtx;
bool load_rasterization_prim;
bool force_sample_iter_shading_rate;
uint32_t db_shader_control; /* DB_SHADER_CONTROL without intrinsic rate overrides */
} ps;
struct {

13
src/amd/vulkan/radv_shader_info.c
View file

@ -644,6 +644,19 @@ gather_shader_info_fs(const struct radv_device *device, const nir_shader *nir,
}
}
/* Disable VRS and use the rates from PS_ITER_SAMPLES if:
*
* - The fragment shader reads gl_SampleMaskIn because the 16-bit sample coverage mask isn't enough for MSAA8x and
* 2x2 coarse shading.
* - On GFX10.3, if the fragment shader requests a fragment interlock execution mode even if the ordered section was
* optimized out, to consistently implement fragmentShadingRateWithFragmentShaderInterlock = VK_FALSE.
*/
info->ps.force_sample_iter_shading_rate =
(info->ps.reads_sample_mask_in && !info->ps.needs_poly_line_smooth) ||
(device->physical_device->rad_info.gfx_level == GFX10_3 &&
(nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered ||
nir->info.fs.pixel_interlock_ordered || nir->info.fs.pixel_interlock_unordered));
/* DB_SHADER_CONTROL based on other fragment shader info fields. */
unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;