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Author SHA1 Message Date
Alyssa Rosenzweig
c78c2e03f4 jay: remove send split hack 
The new partitioning code behaves sensibly here now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:31 +00:00
Alyssa Rosenzweig
04236b3912 jay: merge partition blocks 
The way we construct partitions, it is tricky to avoid empty blocks sometimes
leading to mergeable adjacent blocks. Simplify this at runtime.

Stats are kind of a mixed bag but this is the obvious right thing to do.

simd16:

   Totals:
   Instrs: 2752919 -> 2752284 (-0.02%); split: -0.03%, +0.01%
   CodeSize: 41105312 -> 41096640 (-0.02%); split: -0.03%, +0.01%

   Totals from 236 (8.92% of 2647) affected shaders:
   Instrs: 740015 -> 739380 (-0.09%); split: -0.12%, +0.04%
   CodeSize: 11076496 -> 11067824 (-0.08%); split: -0.11%, +0.04%

simd32:

   Totals:
   Instrs: 4121085 -> 4121638 (+0.01%); split: -0.01%, +0.02%
   CodeSize: 61394672 -> 61404720 (+0.02%); split: -0.00%, +0.02%

   Totals from 145 (5.48% of 2647) affected shaders:
   Instrs: 1104897 -> 1105450 (+0.05%); split: -0.02%, +0.07%
   CodeSize: 16845728 -> 16855776 (+0.06%); split: -0.02%, +0.08%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:31 +00:00
Alyssa Rosenzweig
598931f653 jay: rewrite partition handling 
Jay's novel SSA-based register allocator relies on a fixed partition of Intel
GRFs mapping to logical GPRs.

Previously, Jay used a simple partitioning scheme, which was good enough for
simple compute and fragment shaders, but has both limitations preventing new
feature bring-up and performance issues.

Here we rewrite the Jay partitioning code at the heart of the Jay RA in
order to lift these restrictions and allow fully flexible partitions. This
should be easier to reason about, fix a bunch of issues around simd32 payloads,
enable better performance, etc.

The # of stride 16 GRFs reserved is halved in simd32 mode here to match how
multisampling stuff works, which explains the large simd32-only instruction
count reduction.

While churning all this code, I took the opportunity to break off
jay_partition.c... I think that is better organized and the diff was garbage
otherwise.

SIMD16:
   Totals from 2189 (82.70% of 2647) affected shaders:
   Instrs: 2702159 -> 2670951 (-1.15%); split: -1.41%, +0.26%
   CodeSize: 40296128 -> 39850304 (-1.11%); split: -1.40%, +0.30%

SIMD32:
   Totals from 2373 (89.65% of 2647) affected shaders:
   Instrs: 4559418 -> 4072897 (-10.67%); split: -10.77%, +0.10%
   CodeSize: 68185488 -> 60635616 (-11.07%); split: -11.17%, +0.09%
   Number of spill instructions: 44069 -> 44055 (-0.03%)
   Number of fill instructions: 43292 -> 43278 (-0.03%)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:31 +00:00
Alyssa Rosenzweig
1860e7af30 jay: drop unneeded #include 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:30 +00:00
Alyssa Rosenzweig
fc3fb1c3f9 jay/validate_ra: use jay_def_stride 
higher level than jay_gpr_to_stride

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:30 +00:00
Alyssa Rosenzweig
805fe361a6 jay: stop asking for stride=4 ugpr's 
that doesn't make any sense, and will assert with later changes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:30 +00:00
Alyssa Rosenzweig
dabff53902 jay: pack jay_stride 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:30 +00:00
Alyssa Rosenzweig
8b3fcaf0e3 jay: add zip_ugpr16 instruction 
this will be used to deal with even more simd32 fragment payload pathologies.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:29 +00:00
Alyssa Rosenzweig
de5aedfad9 jay: fix FS reading too many sysvals 
caught in
dEQP-GLES31.functional.texture.texture_buffer.modify.bufferdata.offset_1_alignments
simd32

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:29 +00:00
Alyssa Rosenzweig
64acab1d69 jay/lower_spill: use 1 less temporary 
Spill lowering needs to resreve some registers, but the whole 1.1 GRF business
will be tricky to deal with for future partitioning changes. Fortunately, we can
compact things a bit, using exactly 1 GRF in SIMD16 mode.

SIMD16:

   Totals:
   Instrs: 2752302 -> 2753102 (+0.03%); split: -0.01%, +0.03%
   CodeSize: 41067280 -> 41075568 (+0.02%); split: -0.01%, +0.03%

   Totals from 27 (1.02% of 2647) affected shaders:
   Instrs: 402012 -> 402812 (+0.20%); split: -0.04%, +0.24%
   CodeSize: 6094752 -> 6103040 (+0.14%); split: -0.04%, +0.18%

SIMD32:

   Totals:
   Instrs: 4570539 -> 4572379 (+0.04%); split: -0.09%, +0.13%
   CodeSize: 68437760 -> 68450816 (+0.02%); split: -0.11%, +0.13%

   Totals from 478 (18.06% of 2647) affected shaders:
   Instrs: 3147314 -> 3149154 (+0.06%); split: -0.13%, +0.19%
   CodeSize: 47446400 -> 47459456 (+0.03%); split: -0.16%, +0.19%

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:28 +00:00
Alyssa Rosenzweig
1e7f68d11b jay/register_allocate: remove out of date comment 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:28 +00:00
Alyssa Rosenzweig
56aa083b03 jay/register_allocate: inline silly helper 
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:28 +00:00
Alyssa Rosenzweig
7508b0827c jay/spill: fix reload array size issues 
inspection

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:27 +00:00
Alyssa Rosenzweig
283eef8ac0 jay: legalize shuffle(ugpr) for now 
fixes sascha descriptorindexing .. we'll probably want to revert once divergence
analysis & isel agree but until the multipolygon + anv circus settles this
is better than blowing up. See
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41670 for context.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:27 +00:00
Alyssa Rosenzweig
4a74c773ff jay/liveness: use jay_foreach_preload 
..and explain why.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:27 +00:00
Kenneth Graunke
35470e38ef jay: Don't skip sampler payload copies for 2 or fewer sources 
Sources may be the wrong file for a payload, and this is what copies
them to the correct one.

For example, a 1D shadow comparison may have a UGPR coordinate but
a GPR shadow comparator.  The UGPR needs to be splatted to a full
GPR because the sampler message is divergent.

Unnecessary copies should be easy to propagate away.

Fixes 366 tests in dEQP-VK.texture.shadow.1d.* and
dEQP-VK.pipeline.monolithic.sampler.view_type.1d.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:26 +00:00
Alyssa Rosenzweig
cebc45af43 brw,jay: add use_src_xy prog data field 
to complete the xy/z/w fragcoord set for accurate calculations in jay without
introducing a secondary sideband just for this boolean.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41808>
 2026-05-28 16:23:26 +00:00
Mike Blumenkrantz
caf2c32f42 zink: link up vs COLx vars -> fs BFCx
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
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this fixes some twoside tests

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41863>
 2026-05-28 16:04:41 +00:00
Mike Blumenkrantz
a5146fc0a9 zink: use custom sample locations to (mostly) handle multisample=disabled 
setting all the sample locs to {0.5,0.5} is the same as single-sampled,
which produces the desired output

does not yet handle cases with shader samplemask access

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41862>
 2026-05-28 15:45:07 +00:00
Georg Lehmann
38c4461c78 aco/gfx8: fix 16bit nir_op_ffma 
aco uses the GFX9 opcode names, and GFX8 only has the legacy 16bit fma
that zeros the high register half.

Fixes: 570bfe1ee0 ("ac: handle new float multadd opcodes")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41837>
 2026-05-28 14:52:27 +00:00
Icenowy Zheng
6564b70498 pvr: bump conformance version to 1.4.3.3 
With a few fixes applied, present_id2/wait2 extensions disabled (these
two are not recognized by Vulkan CTS 1.4.3.x) and a fix backported to
the Vulkan CTS, the driver can now pass Vulkan CTS 1.4.3.3.

Bump the conformance version to that value.

The submission link and conformant Vulkan version information in the
current PowerVR driver-specific document is also updated.

Link: https://www.khronos.org/conformance/adopters/conformant-products/vulkan#submission_981
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41786>
 2026-05-28 14:37:04 +00:00
Aitor Camacho
e48b440f1b kk: Correctly report failures when compiling precompiled shaders
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41849>
 2026-05-28 13:50:13 +00:00
Aitor Camacho
ed26c929a8 kk: Add grid struct for dispatches for convenience 
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41849>
 2026-05-28 13:50:13 +00:00
Aitor Camacho
d5805b1eaa kk: Add residency set to queues 
Unsure how needed this is but makes resource visible in Xcode GPU capture

Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41849>
 2026-05-28 13:50:13 +00:00
Aitor Camacho
52168e67b1 kk: Rewrite force position output pass to use lowered io 
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41849>
 2026-05-28 13:50:13 +00:00
Aitor Camacho
dc8f9c91c9 kk: Fix global_store writemask 
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41849>
 2026-05-28 13:50:12 +00:00
jyotiranjan
a5d34f85f8 radv/sqtt: forward zero-submit-count vkQueueSubmit2 for SQTT capture 
Vulkan applications use vkQueueSubmit2(submitCount=0) to signal
throttle fences (e.g. per-image frame-pacing fences). When SQTT
is enabled, sqtt_QueueSubmit2() skips both the bypass path and
the submit loop, so the call is never forwarded and the fence
remains unsignaled.

This causes hangs in drmSyncobjWait (WAIT_FOR_SUBMIT) after capture.

Forward submitCount==0 calls directly to the underlying
QueueSubmit2 to ensure the fence is signaled.

Signed-off-by: jyotiranjan <jyotiranjan.bhuyan@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41766>
 2026-05-28 12:14:59 +00:00
Samuel Pitoiset
05cd2b9509 radv/ci: fix list of expected failures
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41836>
 2026-05-28 11:55:42 +00:00
Samuel Pitoiset
2a2a2127a4 ci: adjust time-trace.sh to not exceed the limit of 255 chars 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
058c8cc999 util: remove declared but unused drirc options 
vk_require_etc2 is used by RADV but it auto-generates the option itself,
so it's safe to remove it from driconf.h.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
c98ea7d2c9 util,asahi: move drirc entries with no_fp16 to asahi 
Asahi is the only driver using them, also rename to asahi_no_fp16.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
7ec22275f9 util,turnip: move drirc entries with vk_dont_care_as_load to Turnip 
Turnip is the only driver using them, also rename to
tu_dont_care_as_load.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
20c77c8ff0 util: remove useless comments in 00-mesa-defaults.conf 
Just make it very simple.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
8c89732e5b util: add a separate file for hasvk drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:47 +00:00
Samuel Pitoiset
1ecb39ce59 util: add a separate file for v3d drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:46 +00:00
Samuel Pitoiset
0de4d3d9c6 util: add a separate file for vmgfx drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:46 +00:00
Samuel Pitoiset
e6730910be util: add a separate file for d3d12 drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:46 +00:00
Samuel Pitoiset
bbc0762223 util: add a separate file for msm drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:46 +00:00
Samuel Pitoiset
88c42258f8 util: add a separate file for r600 drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:45 +00:00
Samuel Pitoiset
f67ca9c529 util: add a separate file for virgl drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:45 +00:00
Samuel Pitoiset
f7b556cf66 util: add a separate file for dozen drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:45 +00:00
Samuel Pitoiset
c2f397c90f util: add a separate file for crocus drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:44 +00:00
Samuel Pitoiset
8fb53f47b9 util: add a separate file for panfrost drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:44 +00:00
Samuel Pitoiset
87860fca06 util: add a separate file for panvk drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:44 +00:00
Samuel Pitoiset
31b7d17da4 util: add a separate file for asahi vulkan drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:44 +00:00
Samuel Pitoiset
46d36e8332 util: add a separate file for asahi drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:43 +00:00
Samuel Pitoiset
a5984c6731 util: add a separate file for iris drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:43 +00:00
Samuel Pitoiset
16f851f71a util: add a separate file for r300 drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:43 +00:00
Samuel Pitoiset
7599fa8322 util: add a separate file for NVK drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:42 +00:00
Samuel Pitoiset
fc7da599fa util: add a separate file for ANV drirc 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41731>
 2026-05-28 11:24:42 +00:00