Commit graph

4732 commits

Author SHA1 Message Date
Alyssa Rosenzweig
59e73674c3 nir: Drop legacy atomics in simple cases
This commit drops legacy atomic support from core passes where we can simply
delete switch cases with no other changes. As such it's separated from the
more complex pass-specific commits for ease of review.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
2023-05-16 22:36:21 +00:00
Alyssa Rosenzweig
0a4c31003d nir: Drop nir_lower_legacy_atomics
No more users.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
2023-05-16 22:36:21 +00:00
Alyssa Rosenzweig
a19660bfc7 nir/lower_printf: Produce unified atomic
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
2023-05-16 22:36:21 +00:00
Alyssa Rosenzweig
6c8e220136 nir/lower_atomics_to_ssbo: Produce unified atomics
This could be simplified if we unified also atomic counters, but that's out of
scope for this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23036>
2023-05-16 22:36:21 +00:00
Emma Anholt
0f25bb8283 nir: Add helpers for lazy var creation.
This should make writing some lowering/meta code easier.  It also keeps
the num_inputs/outputs updated, when sometimes passes forgot to do so (for
example, nir_lower_input_attachments updated for one of the two vars it
creates).  The names of the variables change in many cases, but it's
probably nicer to see "VERT_ATTRIB_POS" than "in_0" or whatever.

I've only converted mesa core (compiler and GL), not all the driver meta
code.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22809>
2023-05-16 18:57:28 +00:00
Konstantin Seurer
40653f0783 nir/lower_shader_calls: Remat derefs earlier
spill_ssa_defs_and_lower_shader_calls can insert phis as well which can
make nir_opt_shrink_stores crash.

Fixes: 200e551c ("nir/lower_shader_calls: Remat derefs before lowering resumes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9003
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23007>
2023-05-16 18:24:17 +00:00
Konstantin Seurer
7b52dcff52 nir/inline_uniforms: Handle num_components > 1
Vulkan UBO loads can have a buffer_index source with more than one component.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23016>
2023-05-15 14:15:02 +00:00
antonino
b5818e2e4f nir: make var arrays large enough in nir_create_passthrough_gs
Because each location has 4 possible different values for location_frac
the arrays need to br 4x the size.

Fixes: d0342e28 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
antonino
8f22669f9b nir: handle interface blocks in copy_vars
Fixes: 99121c9b77 ("nir/gs: fix array type copying for passthrough gs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
antonino
83692bfe30 nir: don't create invalid inputs in nir_create_passthrough_gs
The helper was creating input locations for some builtin bariables.

This caused validation errors in zink because those builtins can't be
used as input.

Fixes: d0342e28b3 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
antonino
78d59ef4b1 nir: use nir_variable_clone in nir_create_passthrough_gs
Some stream out properties where not being copied causing problems in
zink.

Use the appropiate helper instead of copying fields by hand.

Fixes: d0342e28b3 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>
2023-05-15 11:04:41 +00:00
Konstantin Seurer
0cf22f9af3 nir: Make rq_load committed src an index
committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>
2023-05-14 17:28:40 +00:00
Jesse Natalie
4621a6db50 dxil: Use unified atomics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22993>
2023-05-12 16:01:40 -07:00
Alyssa Rosenzweig
fa1962681e nir/validate: Handle unified atomics
nir_validate checks that the format of an atomic (if specified) is compatible
with the atomic operation. For example, we can't fadd R64_UINT texels. The logic
can't be extended as-is to unified atomics because it's split across different
switch cases for different atomic-op intrinsics. So we add our own validation
case, porting over the logic from the separate existing cases below.

(The redundant logic will be deleted once we delete legacy atomics.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
55f7fd6d0d nir/opt_uniform_atomics: Handle unified atomics
This is the one place where using nir_atomic_op instead of nir_op directly is a
little annoying, since we need to translate between the two enums, but it's not
a big deal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
b1fd8d27fc nir/lower_ssbo: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
66f1633ffd nir/lower_io: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
1609b41303 nir/lower_task_shader: Handle unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Jesse Natalie
ca5c869b6d nir: Load/store atomic op indices when lowering image intrinsics
They might not be stored in the same const index after lowering

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
97857731ce nir: Handle unified atomics in simple cases
Lots of passes can be made unified-atomics-aware simply by adding extra cases in
their switch statements. This commit fixes a bunch of passes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
ee6ddce636 ir3: Use unified atomics
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
5c99507028 nir: Add pass to lower atomics to unified
In the future, we'd like to have all drivers only ingest unified atomics, and
all frontends only produce unified atomics, and garbage collect the existing
non-unified atomics. To get to that future, it's a lot nicer to convert drivers
one-by-one. Add a pass to translate old-style atomics to new-style atomics so
drivers can opt-in to the new form one-by-one. Once all drivers are converted,
we can convert producers one-by-one. Finally, we can just drop the calls to the
pass and garbage collect this pass and the old atomics. That's probably a while
out, though, so this will be out bridge to get there.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Alyssa Rosenzweig
d51bc95837 nir: Add unified atomics
Currently, we have an atomic intrinsic for each combination of memory type
(global, shared, image, etc) and atomic operation (add, sub, etc). So for m
types of memory supported by the driver and n atomic opcodes, the driver has to
handle O(mn) intrinsics. This makes a total mess in every single backend I've
looked at, without fail.

It would be a lot nicer to unify the intrinsics. There are two obvious ways:

1. Make the memory type a constant index, keep different intrinsics for
   different operations. The problem with this is that different memory types
   imply different intrinsic signatures (number of sources, etc).  As an
   example, it doesn't make sense to unify global_atomic_amd with
   global_atomic_2x32, as an example. The first takes 3 scalar sources, the
   second takes 1 vector and 1 scalar. Also, in any single backend, there are a
   lot more operations than there are memory types.

2. Make the opcode a constant index, keep different intrinsics for different
   operations. This works well, with one exception: compswap and fcompswap
   take an extra argument that other atomics don't, so there's an extra axis of
   variation for the intrinsic signatures.

So, the solution is to have 2 intrinsics for each memory type -- for atomics
taking 1 argument and atomics taking 2 respectively. Both of these intrinsics
take an nir_atomic_op enum to describe its operation. We don't use a nir_op for
this purpose, as there are some atomics (cmpxchg, inc_wrap, etc) that don't
cleanly map to any ALU op and it would be weird to force it.

The plan is to transition to these new opcodes gradually. This series adds a
lowering pass producing these opcodes from the existing opcodes, so that
backends can opt-in to the new forms one-by-one. Then we can convert backends
separately without any cross-tree flag day. Once everything is converted, we can
convert the producers and core NIR as a flag day, but we have far fewer
producers than backends so this should be fine. Finally we can drop the old
stuff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>
2023-05-12 20:39:46 +00:00
Jesse Natalie
edcecfa817 nir_lower_system_values: Add ASSERTED to assert-only variable
Fixes: 1e0e4657 ("spirv/nir: wire ray interection triangle position fetch")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22994>
2023-05-12 17:09:29 +00:00
Alyssa Rosenzweig
7dfa98abc6 nir: Use nir_block_last_phi_instr more
We have a helper, don't open code it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
aa6bdbd54a nir: Use nir_foreach_phi(_safe)
The pattern shows up all the time open-coded. Use the macro instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
7dc297cc14 nir: Add nir_foreach_phi(_safe) macro
Serious preprocessor voodoo here. There are two tricks here.

1. Iterating only phis. We know that phis come only at the beginning of a block,
   so all over the tree, we open-code iteration like:

      nir_foreach_instr(instr, block) {
         if (instr->type != phi)
            break;

         /* do stuff */
      }

   We can express this equivalently as

      nir_foreach_instr(instr, block)
         if (instr->type != phi)
            break;
         else {
            /* do stuff */
         }

   So, we can define a macro

      #define nir_foreach_phi(instr, block)
         if (instr->type != phi)
            break;
         else

   and then

      nir_foreach_phi(..)
         statement;

   and

      nir_foreach_phi(..) {
         ...
      }

   will expand to the right thing.

2. Automatically getting the phi as a phi. We want the instruction to go to some
   hidden variable, and then automatically insert nir_phi_instr *phi =
   nir_instr_as_phi(instr_internal); We can't do that directly, since we need to
   express the assignment implicitly in the control flow for the above trick to
   work. But we can do it indirectly with a loop initializer.

      for (nir_phi_instr *phi = nir_instr_as_phi(instr_internal); ...)

   That loop needs to break after exactly one iteration. We know that phi
   will always be non-null on its first iteration, since the original
   instruction is non-null, so we can use phi==NULL as a sentinel and express a
   one-iteration loop as for (phi = nonnull; phi != NULL; phi = NULL).

Putting these together gives the macros implemented used.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22967>
2023-05-12 14:02:23 +00:00
Alyssa Rosenzweig
bd466195b9 nir: Make ALU descriptions machine-readable
We already document a lot of ALU opcodes, let's make this machine-readable so we
can put the descriptions in our generated HTML documentation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
2023-05-12 12:11:38 +00:00
Alyssa Rosenzweig
6b4f00a3ac nir: Allow adding descriptions to ALU opcodes
This will let us generate nicer documentation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22929>
2023-05-12 12:11:38 +00:00
Alyssa Rosenzweig
18e19882fa nir: Model AGX-specific multiply-shift-add
Models `(a * b) + (c << d)` in general, as implemented in various forms on AGX.
This will be fused with backend NIR opt algebraic rules, both for the literal
pattern as well as to strength reduce certain multiplications, e.g. replacing
a * 5 with `a + (a << 2)` expressed as imadshl_agx(a, 1, a, 2).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
2023-05-11 09:23:09 -04:00
Alyssa Rosenzweig
0eb5f8e765 nir: Add nir_alu_src_as_uint helper
We have a few ALU instructions that take a constant source. Technically, they
have a swizzle so you can't just nir_src_as_uint them, even though a bunch of
backends do. To help backends do the right thing, add a helper that's just as
easy to use that will chase the swizzle properly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
2023-05-11 09:23:04 -04:00
Konstantin Seurer
0e679e80a9 nir/lower_io: Emit less iadd(x, 0)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22890>
2023-05-10 16:21:34 +00:00
Connor Abbott
6f2be52487 tu, ir3: Handle FDM shader builtins
Also, add the necessary transform to fixup gl_FragCoord.xy.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20304>
2023-05-08 19:59:26 +00:00
Connor Abbott
b474ed1f3a nir, ir3: Add option to use unscaled FragCoord for input attachments
When rendering a scaled tile, we need to use the original, hardware
FragCoord when accessing input attachments that are on-tile (i.e. were
rendered to in a previous subpass) because they are also scaled in the
same way that FragCoord is scaled. For input attachments that aren't
already on-tile, however, we need to use the fixed gl_FragCoord. Add a
new intrinsic and a bitfield of input attachments which should use it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20304>
2023-05-08 19:59:26 +00:00
Konstantin Seurer
5503a08583 nir/lower_fp16_casts: Fix SSA dominance
Fixes: 01dfd65 ("nir: port fp16 casting code from dxil")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22804>
2023-05-07 09:57:29 +00:00
Timur Kristóf
9b6945bb65 amd: Cleanup old GS intrinsics code.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
2023-05-04 19:08:59 +00:00
Timur Kristóf
f66281c7fb amd: Add and implement gs_wave_id sysval.
Contains a global wave ID of legacy GS waves.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
2023-05-04 19:08:58 +00:00
Timur Kristóf
c1591bfc28 amd: Add and implement sendmsg_amd intrinsic.
This intrinsic is going to be used for simplifying GS code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22690>
2023-05-04 19:08:58 +00:00
Illia Polishchuk
0843d4cbc3 nir: switch to a normal sampler for ARB program with not depth textures
It is undefined behavior when an ARB assembly or shadow2d GLSL func
uses SHADOW2D target with a texture in not depth format.
In this case AMD and NVIDIA automatically replaces SHADOW sampler
with a normal sampler and some games like Penumbra Overture which abuses
this UB works fine but breaks with mesa.

Replace the shadow sampler with a normal one here by recompiling
the ARB program variant

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8425
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22147>
2023-05-04 15:43:51 +00:00
Lionel Landwerlin
1e0e4657f9 spirv/nir: wire ray interection triangle position fetch
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <f{merge_request.web_url}>
2023-05-04 11:25:41 +00:00
David Heidelberg
1c1855cc00 nir/lower_io_to_vector: initialize base
Prevent GCC warning:
```
[230/1401] Compiling C object src/compiler/nir/libnir.a.p/nir_lower_io_to_vector.c.o
In function 'get_flat_type',
    inlined from 'create_new_io_vars' at ../src/compiler/nir/nir_lower_io_to_vector.c:300:10:
../src/compiler/nir/nir_lower_io_to_vector.c:208:14: warning: 'base' may be used uninitialized [-Wmaybe-uninitialized]
  208 |       return glsl_array_type(glsl_vector_type(base, 4), slots, 0);
      |              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/compiler/nir/nir_lower_io_to_vector.c: In function 'create_new_io_vars':
../src/compiler/nir/nir_lower_io_to_vector.c:163:24: note: 'base' was declared here
  163 |    enum glsl_base_type base;
      |                        ^~~~
```

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8957

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22840>
2023-05-04 03:44:00 +00:00
Marek Olšák
820c50ada3 nir: rename ACCESS_STREAM_CACHE_POLICY -> ACCESS_NON_TEMPORAL and document
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22769>
2023-05-04 01:55:22 +00:00
Georg Lehmann
b93c92eba3 nir: lower ballot_bit_count_exclusive/inclusive to mbcnt_amd
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22783>
2023-05-03 10:39:20 +00:00
Lionel Landwerlin
53605f226b nir/lower_non_uniform_access: add get_ssbo_size handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22793>
2023-05-02 16:27:15 +00:00
Erik Faye-Lund
955797d015 nir: fix constant-folding of 64-bit fpow
We need to do full pow if 64-bit, and we can do fpow() otherwise. Not
the other way around.

Fixes: 9076c4e289 ("nir: update opcode definitions for different bit sizes")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22774>
2023-05-02 07:53:51 +00:00
Lionel Landwerlin
d6e9479d4b nir/divergence: add missing load_global_constant_* intrinsics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
2023-04-27 09:08:03 +00:00
Erik Faye-Lund
0a718c9354 nir: clean up white-space in deref-printing
Without this, we get some trailing spaces in some cases, and some
double space in some other cases. Let's clean that up a bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22550>
2023-04-27 05:39:57 +00:00
Erik Faye-Lund
4e8b532db3 nir: remove nir_state_slot::swizzle
This is only ever written to, never read from. Let's just get rid of it!

This also saves us a few needless includes.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22620>
2023-04-26 05:51:39 +00:00
Qiang Yu
eb1fe8c32f nir: add nir_export_dual_src_blend_amd intrinsic
For GFX11 export dual source blend outputs when ACO.
ACO need a pseudo instruction to emit a block of
code which can't be done in nir currently.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22199>
2023-04-26 03:27:26 +00:00
antonino
a0645e3383 nir/zink: use sysvals in nir_create_passthrough_gs
Previously the passthrough gs shader loaded some values with uniform
loads using sevaral hardcoded values.

This was not flexible for other drivers and started becoming too
unflexible for zink itself.

Use system values instead and use a lowering pass in zink.

Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22667>
2023-04-25 13:11:59 +00:00