ES version was missed from extension table
Fixes: 2ce20170 ("mesa: Add support for GL_EXT_shader_clock")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37794>
(cherry picked from commit a8fb3671e8)
ES version was missed from extension table
Fixes: c5500cd1 ("mesa: Add support for GL_EXT_shader_realtime_clock")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37794>
(cherry picked from commit 09d86f9863)
We need to return true if we need the companion batch.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e60416b4e4 ("anv: use companion batch for operations with HIZ/STC_CCS destination")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37797>
(cherry picked from commit 196c7903b9)
All vtn_bindgen2-generated files use the same 'vtn_bindgen_dummy' struct
name. When linking more than one file (like in panfrost), the
constructor and destructor symbols collide and every instance ends up
running the same initialization. In panfrost, this results in us
dropping any printf format strings that don't occur in v6.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: b7447a94c8 ("vtn: add vtn_bindgen2 tool")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37798>
(cherry picked from commit d600cd4c91)
When there's only blend mode updates (e.g. CB_BLEND_EQUATIONS not
covered by fs_user_dirty check), we have to set dcd0_dirty for the
relevant CB updates. Otherwise, we might miss to clear FPK. On the
other hand, this also optimizes to set FPK in the reverse mutation, so
that new draws no longer depending on the previous tile buffer can
benefit from FPK.
Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37760>
(cherry picked from commit 98a6825d35)
This state combination wedges something in GPU causing hang.
Forcing A6XX_LATE_Z prevents it. Prop driver does the same.
CC: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37765>
(cherry picked from commit 02138d96fd)
anv_state::offset in the context of anv_state_pool is equal to the offset from
the begining of block_pool + start_offset.
Like it is set in anv_state_pool_alloc_no_vg() in the path that allocs a new
block in anv_block_pool.
As anv_state_pool_return_chunk() expects only the offset from the begining of
anv_block_pool so here subtracting to make the path that grabs a larger chunk of
memory of the pool and split into smaler chunks to properly work.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
(cherry picked from commit a90d8fc08e)
Only 3 pools sets a value different than zero to start_offset so that might be
a issue that was being hidden by luck.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
(cherry picked from commit 4ca18c09c1)
struct anv_state::offset and struct anv_block_pool::max_size are 64bits so these
parameters should also be 64bit or risk overflow.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37669>
(cherry picked from commit ad62911683)
This can trigger an assert otherwise. The space reserved before
executing DGC IBs is an arbitrary number which should be large enough
in all cases.
Found this while implementing descriptor heap.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37681>
(cherry picked from commit 874bc09537)
If there are no leaves, the root node bounds still span -inf/inf.
Making empty BLASs infinite-sized guarantees ray traversal needs to
enter the BLAS (and immediately exit because it's empty). Remove the
BLAS from the BVH entirely by marking its bounds as NaN. As a bonus,
this works around RADV encountering issues in Silent Hill 2 on RDNA4 due
to infinite-sized BVHs.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37492>
(cherry picked from commit 52c7b0d20c)
Xwayland seems to mix implicit and explicit sync, depending on client
app. This trips up the heuristic that disables implicit sync once it
starts seeing app using explicit sync. This is not typical behavior,
so add a driconf override to disable the heuristic.
Fixes: 137cd3b0fa ("freedreno/drm: Move no_implicit_sync accounting")
Cc: mesa-stable
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37703>
(cherry picked from commit e60d34fa78)
This also includes support for the new job cookie system, verifying that jobs
running originate from the claimed source. This is useful internally but won't
affect users, unlike the feature in the title :)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37609>
(cherry picked from commit c3957860b8)
Commit 2aaa6ebb "build/amd: add amd-use-llvm build option"
allows to build radeonsi and radv without LLVM dependency
so LLVM constraint is applicable when amd-use-llvm=true
Fixes: 82047fa8 ("amd: drop support for LLVM 15, 16, 17")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37695>
(cherry picked from commit dd2476a257)
float_controls2 may have marked these as needing to preserve NaN or
other values. If so, our newly contracted ffma needs to as well.
Fixes dEQP-VK.spirv_assembly.instruction.compute.float_controls2.*.input_args.mat_det_testedWithout_NotNan*
when nir_opt_algebraic is run after this pass.
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36750>
(cherry picked from commit 1b0808adf3)
For some reason we missed adding this. This prevents some asserts
from triggering when I call divergence analysis at certain points
in an upcoming patch.
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36750>
(cherry picked from commit 25cb6dfbf7)
For an image created either without a modifier to share or as the
destination image to get rid of compression by re-allocation, it
should have compression disabled.
Close: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13729
(Fix firefox misrendering when gfx.wayland.hdr option is true)
Backport-to: 25.2
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37098>
(cherry picked from commit 5aa4dc7f77)
The functionality is provided by isl_surf_supports_ccs().
Also, move the protected content restriction to
iris_resource_configure_aux(). I'm not aware of any reason protected
content wouldn't support CCS. However, to keep this series simple,
enabling that combination is left for another time.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
Allow CCS for non-display linear surfaces in isl_surf_supports_ccs().
We're going to rely more on the helper to determine CCS-enabling for Xe2
on iris.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
The compression format is only used during rendering.
This prevents drivers from hitting an unreachable when we start enabling
CCS on linear surfaces which may have non-renderable and non-pow2 formats.
For now, continue to use the surface format instead of the view format
to look up the CMF. This strategy should return the optimal CMF for
compressed surfaces that undergo redescription during copies.
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
On XeKMD, BOs need to be created with a vm_id of zero in order to get
prime handles. That only occurs if the image was created with
PIPE_BIND_SHARED/BO_ALLOC_SHARED. Ensure that shareable images have this
flag in iris_flush_resource().
Fixes the dmabufshare demo on BMG with INTEL_DEBUG=noccs and mesa hacked
to disable suballocation.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13511
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37168>
