Commit graph

93348 commits

Author SHA1 Message Date
Topi Pohjolainen
a9c59c10a5 i965/miptree: Separate src and dst slice specifiers in slice copy
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Topi Pohjolainen
920c8e89c5 i965/miptree: Clarify face/level/layer in slice copy
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-19 22:18:53 +03:00
Jonas Kulla
a52ee32a9a anv: Fix L3 cache programming on Bay Trail
Valid values for URBAllocation start at 32, so substract that
before programming the register.

This was missed when porting from the GL driver.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-19 12:05:52 -07:00
Marek Olšák
3fc99f1299 radeonsi: fix dumping shader descriptors into ddebug logs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:16:20 +02:00
Marek Olšák
f9dc29a9a5 radeonsi: add a workaround for inexact SNORM8 blitting again
GFX9 is affected.

We only have tests for GL_x_SNORM where x is R8, RG8, RGB8, and RGBA8.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
0f827b51c0 radeonsi/gfx9: fix TC-compatible stencil compression
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
8a264dd829 radeonsi/gfx9: fix TXF_LZ with 1D textures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
353b60cab5 radeonsi/gfx9: disable sparse buffers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
064f07fef3 ac/sid.h: don't use parentheses in PKT3_RELEASE_MEM definition
The parses skips the line if it contains parentheses.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
ed291cea3d ac: parse EVENT_WRITE_EOP, RELEASE_MEM, WAIT_REG_MEM, NOWHERE
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:15:36 +02:00
Marek Olšák
66b6babbea st/mesa: simplify returning GL_VENDOR
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:09:52 +02:00
Marek Olšák
92b4ca4550 st/mesa: remove the "Gallium 0.4 on" prefix from GL_RENDERER
If you want to keep it for your driver, please raise your hand.
The prefix will probably have to be added into the driver instead of here.

I cringe when I look at my long renderer string:
  Gallium 0.4 on AMD Radeon R9 Fury Series (DRM 3.17.0 / 4.11.0-staging-01277-gab25a9e, LLVM 5.0.0)

I'm sincerely sorry for all apps that detect Mesa by expecting "Gallium"
in the string.

Reviewed-by: Eric Anholt <eric@anholt.net>
2017-06-19 20:09:52 +02:00
Marek Olšák
61dc2c964e st/mesa: don't update MSAA states for GL_FRAMEBUFFER_SRGB
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 20:09:52 +02:00
Kenneth Graunke
6a7c5257ca i965: Ignore anisotropic filtering in nearest mode.
This fixes both Europa Universalis IV and Stellaris rendering on i965.
This was tested on SKL.

This fix was discovered by Jakub Szuppe at Stream HPC
(https://streamhpc.com/).

bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96958
bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95530
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
2017-06-19 10:09:06 -07:00
Iago Toral Quiroga
b70d6a2de1 glsl: gl_Max{Vertex,Fragment}UniformComponents exist in all desktop GL versions
The current implementation assumed that these were replaced in GLSL >= 4.10
by gl_Max{Vertex,Fragment}UniformVectors, however this is not true: both
built-ins should be produced from GLSL 4.10 onwards.

This was raised by new CTS tests that are in development.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-06-19 14:43:54 +02:00
Emil Velikov
4a7222518d docs: update calendar, add news item and link release notes for 17.1.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-19 12:23:07 +01:00
Emil Velikov
42098bf9b2 docs: add sha256 checksums for 17.1.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-19 12:20:52 +01:00
Emil Velikov
b55dfb7be3 docs: add release notes for 17.1.3
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-19 12:20:51 +01:00
Nicolai Hähnle
b28938ffce st/glsl_to_tgsi: use correct writemask when converting generic intrinsics
This fixes a bug when lowering ballotARB: previously, using writemask 0xf,
emit_asm would create TGSI_OPCODE_BALLOT instructions that span two registers
to cover 4 64-bit channels. This could trample over other a neighbouring
temporary.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101360
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-19 12:07:05 +02:00
Nicolai Hähnle
25e5534734 gallium/radeon/gfx9: fix PBO texture uploads to compressed textures
st/mesa creates a surface that reinterprets the compressed blocks as
RGBA16UI or RGBA32UI. We have to adjust width0 & height0 accordingly to
avoid out-of-bounds memory accesses by CB.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-19 12:05:15 +02:00
Nicolai Hähnle
4d5bb1b987 r600: fix off-by-one in egd_tables.py
Port of the corresponding fix in sid_tables.py.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-19 12:05:12 +02:00
Nicolai Hähnle
67e49a7f65 amd/common: fix off-by-one in sid_tables.py
The very last entry in the sid_strings_offsets table ended up missing,
leading to out-of-bounds reads and potential crashes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-19 12:03:59 +02:00
Iago Toral Quiroga
b72b7c541d i965: update MaxTextureRectSize to match PRMs and comply with OpenGL 4.1+
We were exposing 4096, but we can do up to 8192 in Gen4-6 and up to
16384 in gen7+. OpenGL 4.1+ requires at least 16384.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-19 07:55:48 +02:00
Samuel Pitoiset
10d104207a mesa: add KHR_no_error support for gl*UniformHandleui64*ARB
Similar to _mesa_uniform() except that we have to call
validate_uniform_parameters() instead of validate_uniform().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:21:05 +02:00
Samuel Pitoiset
304de4edb9 mesa: add KHR_no_error support for glGetImageHandleARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:21:04 +02:00
Samuel Pitoiset
530ff887eb mesa: add KHR_no_error support for glGetTexture*HandleARB()
It would be nice to have a no_error path for
_mesa_test_texobj_completeness() because this function doesn't
only test if the texture is complete.

Anyway, that seems enough for now and a bunch of checks are
skipped with this patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:21:01 +02:00
Samuel Pitoiset
0fb2c89c71 mesa: add KHR_no_error support for glMake{Image,Texture}Handle*ResidentARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:20:59 +02:00
Samuel Pitoiset
d7bee4a022 mesa: add KHR_no_error support for glIs{Image,Texture}HandleResidentARB()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-06-18 14:20:57 +02:00
Samuel Pitoiset
6ff6863c32 radeonsi: reduce overhead for resident textures which need color decompression
This is done by introducing a separate list.

si_decompress_textures() is now 5x faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:38 +02:00
Samuel Pitoiset
06ed251c32 radeonsi: reduce overhead for resident textures which need depth decompression
This is done by introducing a separate list.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:36 +02:00
Samuel Pitoiset
705a6a560e radeonsi: use util_dynarray_foreach for bindless resources
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:34 +02:00
Samuel Pitoiset
db73595018 mesa/util: add util_dynarray_clear() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:10:32 +02:00
Samuel Pitoiset
8d9e76ce1f gallium/radeon: add a new HUD query for the number of resident handles
Useful for debugging performance issues when ARB_bindless_texture
is enabled. This query doesn't make a distinction between texture
and image handles.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-18 14:08:08 +02:00
Topi Pohjolainen
e08171ef53 i965/gen4: Refactor depth/stencil rebase
Effectively there is the same code twice, once for depth and
again for stencil.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
84b195b361 i965: Drop depth/stencil miptree pointers in alignment workaround
In brw_workaround_depthstencil_alignment() corresponding
renderbuffers are always set to refer to the same temp miptrees.
There is no need to carry them in context.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
cd0804c359 i965/gen4: Simplify depth/stencil invalidate check
There is no separate stencil on gen < 6.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
bb5d3fe96a i965/gen4: Remove redundant check for depth when rebasing stencil
In case of gen < 6 stencil (if present) is always combined with
depth. Both stencil and depth attachments point to the same
physical surface.
Alignment workaround starts by considering depth and updates
stencil accordingly. Current logic continues with stencil and
in vain considers the case where depth would refer to different
surface than stencil.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Topi Pohjolainen
04524ac0d4 i965/gen4: Remove non-existing stencil and hiz buffer setup
Separate stencil and hiz are only enabled for gen6+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-18 10:46:44 +03:00
Mauro Rossi
58d337941e android: ac: add missing libdrm_amdgpu shared dependency
Fixes building errors in amd/common:

target  C: libmesa_amd_common <= external/mesa/src/amd/common/ac_gpu_info.c
...
target  C: libmesa_amd_common <= external/mesa/src/amd/common/ac_surface.c
...

external/mesa/src/amd/common/ac_gpu_info.h:31:10: fatal error: 'amdgpu.h' file not found
         ^
2 errors

Fixes: 98a2492 ("ac_surface: use radeon_info from ac_gpu_info")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2017-06-17 18:38:31 +01:00
Emil Velikov
68aa39d5c2 r600: include libelf headers only as needed
Headers are required only when building with OpenCL. As we're building
w/o it libelf may be missing, hence we'll error out as below:

src/gallium/drivers/r600/evergreen_compute.c:27:10:
fatal error: 'gelf.h' file not found
         ^
1 error generated.

Fixes: d96a210842 ("r600g,compute: provide local copy of functions from
ac_binary.c")
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-17 16:57:18 +01:00
Emil Velikov
1f958c1337 radeonsi: include ac_binary.h for struct ac_shader_binary
The header embeds the struct so it needs the header inclusion instead of
the dummy forward declaration.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Tom Stellard <tstellar@redhat.com>
Fixes: 32206c5e56 ("radeonsi: Add radeon_shader_binary member to struct
si_shader")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:38:02 +01:00
Emil Velikov
7e1c42cf89 r600, radeon: move radeon_shader_binary_{init,clean} back to radeon
Those are used by r600 and radeonsi, so moving them within the former
was a bad idea.

Fixes: d96a210842 ("r600g,compute: provide local copy of functions
from ac_binary.c")
Cc: Jan Vesely <jan.vesely@rutgers.edu>
Cc: Aaron Watry <awatry@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:37:58 +01:00
Emil Velikov
84bf7e5ad6 ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"
The commit did not add the relevant includes - in particular
stdint.h and stdbool.h for the respective standard types.

At the same time, the amdgpu_device_handle typedef redeclaration was
off.

Fixes: 81945ded0d ("ac: remove amdgpu.h dependency")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101471
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Gregor Münch <gr.muench@gmail.com>
Reported-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reported-by: Gregor Münch <gr.muench@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-06-17 11:37:51 +01:00
Topi Pohjolainen
6967285981 i965/gen4: Set depth offset when there is stencil attachment only
Current version fails to set depthstencil.depth_offset when there
is only stencil attachment (it does set the intra tile offsets
though). Fixes piglits:

g45,g965,ilk:   depthstencil-render-miplevels 1024 s=z24_s8
g45,ilk:        depthstencil-render-miplevels 273 s=z24_s8

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Topi Pohjolainen
a8e89cd539 i965/gen6: Remove dead code in hiz surface setup
In intel_hiz_miptree_buf_create() the miptree is unconditionally
created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Topi Pohjolainen
0d1af164e1 intel/isl/gen6: Allow arrayed stencil
Nothing prevents arrayed stencil surfaces even though hardware
doesn't support mipmapping.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-17 06:38:56 +03:00
Brian Paul
e3f5b8ac16 svga: add new num-failed-allocations HUD query
This counter is incremented if we fail to allocate memory for
vertex/index/const buffers, textures, etc.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-16 17:04:08 -06:00
Brian Paul
b27281c110 gallium/hud: support GALLIUM_HUD_DUMP_DIR feature on Windows
Use a dummy implementation of the access() function.  Use \ path separator.
Add a few comments.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-06-16 17:04:02 -06:00
Brian Paul
d6cb912d65 svga: add a few minor comments
Trivial.
2017-06-16 17:03:01 -06:00
Brian Paul
15f4c3ada4 mesa: whitespace fixes in enable.c
Remove trailing whitespace, replace tabs w/ spaces, etc.  Trivial.
2017-06-16 17:03:01 -06:00