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anv: Fix L3 cache programming on Bay Trail

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Valid values for URBAllocation start at 32, so substract that
before programming the register.

This was missed when porting from the GL driver.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jonas Kulla 2017-06-19 19:46:23 +02:00 • committed by Jason Ekstrand
parent 3fc99f1299
commit a52ee32a9a
1 changed files with 1 additions and 1 deletions
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2
src/intel/vulkan/genX_cmd_buffer.c
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@ -835,7 +835,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
anv_pack_struct(&l3cr2, GENX(L3CNTLREG2),
.SLMEnable = has_slm,
.URBLowBandwidth = urb_low_bw,
.URBAllocation = cfg->n[GEN_L3P_URB],
.URBAllocation = cfg->n[GEN_L3P_URB] - n0_urb,
#if !GEN_IS_HASWELL
.ALLAllocation = cfg->n[GEN_L3P_ALL],
#endif