The diff looks like it moves code that I didn't touch.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
One more CFL ID added to spec.
Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Starting with a6xx, half and full precision registers conflict. Which
makes things a bit more efficient, ie. if some parts of the shader are
heavy on half-precision and others on full precision, you don't have to
allocate the worst case for both. But it means we need to setup some
additional conflicts.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Collapse is_temp() into it's only callsite, and pass compiler object as
struct rather than void. Just cleanups to reduce noise in next patch.
Signed-off-by: Rob Clark <robdclark@gmail.com>
We originally did this because at the time we didn't know all the
bitfields to configure where various frag shader sysval's went. But
we do.
So switch to using sysvals for all the frag shader inputs.
Signed-off-by: Rob Clark <robdclark@gmail.com>
create_input()/create_input_compmask() should take the ctx as arg,
rather than block, to enforce that all inputs are created in the first
block, so that RA sees them as live at the start of the shader.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Make it more clear that this is varying fetch related. Also fixup some
comments. Just cleanup for next patches.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Used internally in freedreno/ir3 for the vec2 value that hw passes to
shader to use as coordinate for bary.f (varying fetch) instruction.
This is not the same as SYSTEM_VALUE_FRAG_COORD.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.
The new version of the ext got published in specification 1.1.81.
Sending to stable since the only known user is DXVK, which needs
this for correctness.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: 18.2 <mesa-stable@lists.freedesktop.org>
Following patches will be doing further cleanup after calling
fd_context_destroy() so it is easier if we move the free() into
the per-gen backend code.
Signed-off-by: Rob Clark <robdclark@gmail.com>
this patch brings a number of changes to ir2:
-ir2 now generates CF clauses as necessary during assembly. this simplifies
fd2_program/fd2_compiler and is necessary to implement optimization passes
-ir2 now has separate vector/scalar instructions. this will make it easier
to implementing scheduling of scalar+vector instructions together. dst_reg
is also now seperate from src registers instead of a single list
-ir2 now implements register allocation. this makes it possible to compile
shaders which have more than 64 TGSI registers
-ir2 now implements the following optimizations: removal of IN/OUT MOV
instructions generated by TGSI and removal of unused instructions when
some exports are disabled
-ir2 now allows full 8-bit index for constants
-ir2_alloc no longer allocates 4 times too many bytes
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
In environments where we cannot cache, e.g. Android (no homedir),
ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the
startup cost of creating a device in radv is rather high, due
to compiling all possible built-in pipelines up front. This meant
depending on the CPU a 1-4 sec cost of creating a Device.
For CTS this cost is unacceptable, and likely for starting random
apps too.
So if there is no cache, with this patch radv will compile shaders
on demand. Once there is a cache from the first run, even if
incomplete, the driver knows that it can likely write the cache
and precompiles everything.
Note that I did not switch the buffer and itob/btoi compute pipelines
to on-demand, since you cannot really do anything in Vulkan without
them and there are only a few.
This reduces the CTS runtime for the no caches scenario on my
threadripper from 32 minutes to 8 minutes.
Reviewed-by: Dave Airlie <airlied@redhat.com>
From AppVeyor #8582, it seems that MSVC doesn't like uint, so this
patch replaces it with unsigned.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Meson now uses python3, so let's add a block for Autotools, move that
line into the buildsys-specific blocks, and set the correct version for
Meson.
Fixes: 2ee1c86d71 "meson: Build with Python 3"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
This is clearly a copy-paste error; if we validate the reladdr2-pointer,
we don't want to traverse to the reladdr-pointer. Especially since the
check above shows that reladdr could be NULL here.
Noticed by Coverity.
CID: 1438389, 1438390
Fixes: 568bda2f2d ("mesa/st/glsl_to_tgsi: Split arrays whose elements are only accessed directly")
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gert Wollny <gw.fossdev@gmail.com>
