fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 04:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4
149838 commits 66 branches 934 tags 1 GiB
Commit graph

149838 commits

This branch
This branch
All branches
Author SHA1 Message Date
Jesse Natalie
c7bd1f0720 microsoft/compiler: Only prep phis for the current function 
Fixes: 41af9620 ("microsoft/compiler: Emit all NIR functions into the DXIL module")
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Reviewed-By: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14837>
(cherry picked from commit 0c711dc823)
 2022-02-07 21:36:02 -08:00
Mike Blumenkrantz
88762cf59b zink: add VK_BUFFER_USAGE_CONDITIONAL_RENDERING_BIT_EXT for query binds 
required by spec

cc: mesa-stable

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14853>
(cherry picked from commit 1e96542390)
 2022-02-07 21:36:01 -08:00
Dylan Baker
6420dc86cf .pick_status.json: Update to 8335fdfeaf 2022-02-07 21:35:59 -08:00
Rhys Perry
a58a01050c aco: don't encode src2 for v_writelane_b32_e64 
Encoding src2 doesn't cause issues for print_asm() because we have a
workaround there, but it does for RGP and it seems the developers are not
interested in fixing it.

https://github.com/GPUOpen-Tools/radeon_gpu_profiler/issues/61

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14832>
(cherry picked from commit 0447a2303f)
 2022-02-03 10:32:02 -08:00
Pierre-Eric Pelloux-Prayer
b6e296f823 radeonsi: limit loop unrolling for LLVM < 13 
Without this change LLVM 12 hits this error:

"""
LLVM ERROR: Error while trying to spill SGPR0_SGPR1 from class SReg_64:
Cannot scavenge register without an emergency spill slot!
"""

when running glcts KHR-GL46.arrays_of_arrays_gl.AtomicUsage test.

Fixes: 9ff086052a ("radeonsi: unroll loops of up to 128 iterations")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14848>
(cherry picked from commit eaa87b1a46)
 2022-02-03 10:32:02 -08:00
Iago Toral Quiroga
fabb6b5c5e broadcom/compiler: fix offset alignment for ldunifa when skipping 
The intention was to align the address to 4 bytes (32-bit), not
16 bytes.

Fixes: bdb6201ea1 ("broadcom/compiler: use ldunifa with unaligned constant offset")

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14830>
(cherry picked from commit 0a8449b07c)
 2022-02-03 10:32:01 -08:00
Mike Blumenkrantz
0ec3de0563 llvmpipe: disable PIPE_SHADER_CAP_FP16_CONST_BUFFERS 
this cap is broken

cc: mesa-stable

fixes:
GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUnifor

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14835>
(cherry picked from commit 9a75392cd8)
 2022-02-03 10:32:01 -08:00
Mike Blumenkrantz
b2be43a192 zink: disable PIPE_SHADER_CAP_FP16_CONST_BUFFERS 
this cap is broken

cc: mesa-stable

fixes:
GTF-GL46.gtf21.GL2Tests.glGetUniform.glGetUniform

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14835>
(cherry picked from commit 9a38dab2d1)
 2022-02-03 10:32:00 -08:00
Dylan Baker
9e17fcbed2 .pick_status.json: Update to 0447a2303f 2022-02-03 10:31:57 -08:00
Dylan Baker
c69a870f86 VERSION: bump for 22.0.0-rc1 release 2022-02-02 15:15:29 -08:00
Bas Nieuwenhuizen
0395c483d4 radv: Handle SDMA for padding. 
Also assert that nobody actually needs to chain an SDMA IB because we have
not implemented non-PKT3 chaining.

Fixes: ef40f2ccc2 ("radv/amdgpu: Fix handling of IB alignment > 4 words.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5923
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14781>
 2022-02-02 22:23:17 +00:00
Emma Anholt
dbcdededb2 intel: Add missing dep of gen_*_header.py on utils.py. 
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
 2022-02-02 11:21:57 -08:00
Emma Anholt
3d5ee08c15 freedreno/isaspec: Add missing dep of encode.py/decode.py calls on isa.py 
Fixes: #5921
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14725>
 2022-02-02 11:21:56 -08:00
Caio Oliveira
242c7a6513 anv: Add experimental support for VK_NV_mesh_shader 
Enable setting ANV_EXPERIMENTAL_NV_MESH_SHADER=1 environment variable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Caio Oliveira
d9416cd8bd intel/dev: Enable Mesh Shading for DG2 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
da273b2b7b anv: Put first few push constants directly into Task/Mesh InlineData 
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
27c32fd14b anv: include ClipDistance array in mesh shader per-vertex output 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
c95b4ac2eb anv: tell the hardware about gl_[Clip|Cull]Distance in mesh shaders 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
bbde9f2448 anv: Implement indirect dispatch for Mesh pipeline 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
18e628135d anv: Add support for UBOs, SSBOs and push constants in Mesh pipeline 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
f12f5ae2f8 anv: Add support for non-zero firstTask in vkCmdDrawMeshTasksNV 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Marcin Ślusarz
97da3e0814 anv: Enable conditional rendering in vkCmdDrawMeshTasksNV 
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Caio Oliveira
ef04caea9b anv: Implement Mesh Shading pipeline 
The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Caio Oliveira
325ac235a7 anv: Add boilerplate for VK_NV_mesh_shader 
Use minimum values for the properties.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Caio Oliveira
c93cbc77f7 intel/common: Add helper for URB allocation in Mesh pipeline 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Caio Marcelo de Oliveira Filho
b01c73fd0a intel: Add INTEL_URB_DEREF_BLOCK_SIZE_MESH 
And corresponding value in XML.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
 2022-02-02 18:17:57 +00:00
Alyssa Rosenzweig
4c38229ac1 pan/va: Add ARM_shader_framebuffer_fetch asm test 
This is a nontrivial chunk of code that makes for a nice dis/assembler test
case (and caught a bug already...). Add it to the observatory.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
a99eac8a49 pan/va: Handle shift lanes in assembler 
Noticed in a program using ARM_shader_framebuffer_fetch.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
b3c7159308 pan/va: Add lots of swizzle assembler tests 
The swizzle handling in ISA.xml was broken in a bunch of place. Now that
we've fixed these issues, let's add tons of tests to validate.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
57bb3c7158 pan/va: Add 2-channel 8-bit swizzles for conversions 
Instructions like V2S8_TO_V2S16 need a special 4-bit special selecting any two
bytes. The definition is the same as Bifrost. Let's call this a half-swizzle
since we need a name, and it is indeed half a swizzle...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
cdb7c4e42d pan/va: Vectorize 8->16-bit conversions 
Matches Bifrost, too.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
441c47ff74 pan/va: Fix lane select for [US]_TO_[USF]32 
The lane select is in bit 28, this is covered by the "16-bit swizzle" mode.
However, the source type isn't inferred from the name in valhall.py, so
explicitly annotate the source as 16-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
46cd0ddcb6 pan/va: Fix MKVEC.v2i16 lane select 
The lanes are at bit 28 and bit 26 respectively. This matches the 16-bit "swizzle" encoding. In general the handling of widens/swizzles/lane/lanes on Valhall is rather confused but... one problem at a time.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
a95ca2402c pan/va: Test LD_TILE assembly 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
dc61e362f4 pan/va: Add missing fields to LD_TILE 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
0f9007985d pan/va: Add missing <clamp/> to V2F32_TO_V2F16 
For parity with Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Alyssa Rosenzweig
3fff018c98 pan/va: Add .absolute bit to BRANCHZI 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14833>
 2022-02-02 17:42:01 +00:00
Lionel Landwerlin
665ffd4bf9 anv: Update VK_KHR_fragment_shading_rate for newer HW 
Per primitive & attachment shading rate support added.

v2: Rebase on KHR_dynamic_rendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
fc837e9f8b anv/pass: rely on precomputed dynamic rendering pass/subpass more 
For instance, the current code in genX_cmd_buffer.c assumes that the
depth/stencil attachments & resolves will be at the end of all
attachments, but that won't be the case anymore with fragment rate
shading.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
16763e8b8e anv: force primitive shading rate write in last geometry stage 
v2: Use new helper to check if stage supports variable shading rate
    setting

v3: Update comment & iterate backward (Caio)
    Apply only to relevant platforms (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
0cd93c59ef intel/compiler: add primitive rate output support 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
cebf284ac1 intel/compiler: add a new pass to lower shading rate into HW format 
Rework:
 * Jason: Modernize brw_nir_lower_shading_rate_output:
   1. Use nir_shader_instructions_pass()
   2. Use *_imm builder helpers.
   3. Use nir_intrinsic_base() instead of ->const_index[0]

v2: Also lower loads (Caio)

v3: Update stage check to trigger lowering (Caio)

v4: Assert on != MESH (Caio)

v5: Fixup instruction insertion (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
e227bb9fd5 nir/builder: add ishl_imm helper 
v2: add (y >= x->bit_size) condition (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
3ab7f4471c isl: disable CPB surface compression 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
dff08cbf8e isl: add support for coarse pixel control surfaces 
Those surfaces are used as attachment to rendering passes and describe
the rate of coarse pixel shading for the pass.

v2: Move CPB_BIT tile filtering to isl_gfx125_filter_tiling() (Nanley)

v3: Drop unused macro (Nanley)
    s/isl_to_gen/isl_encode/ (Nanley)
    Remove pitch alignment 128B constraint already covered by tiling (Nanley)
    Move some asserts together (Nanley)

v4: Disable miptail for now (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
8d90fe587f intel/dev: details CPS feature support 
DG2 introduces per primitive coarse pixel settings (in stages
preceding the PS shader) and also a control surface specifying the
rate at through the resulting surface.

v2: update comment (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
8bdbc93a9d genxml: add new 3DSTATE_PS_EXTRA bit 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
ea71fb0b4b genxml: gen12.5 changes for CPS 
v2: Make genxml look more like BSpec (Caio)
    Fixup X_Focal/Y_Focal entries (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Lionel Landwerlin
7d8884800e compiler: add VARYING bit for primitive shading rate 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13739>
 2022-02-02 17:09:46 +00:00
Filip Gawin
9322b76fc4 r300: replace recursive calls with loops 
Recursive "loops" tend to be more difficult to follow
and understand. Additionally iterative approach should be
nicer for compiler. (Less to allocate on stack and easier to optimize)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13226>
 2022-02-02 16:50:03 +00:00