Commit graph

96172 commits

Author SHA1 Message Date
Jason Ekstrand
be8d009908 nir: Add a array-of-vector variable shrinking pass
This pass looks for variables with vector or array-of-vector types and
narrows the type to only the components used.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:46:56 -05:00
Jason Ekstrand
02a5442dd7 intel/nir: Use the new structure and array splitting passes
We call structure splitting once because it is guaranteed to split all
the structures in the entire shader in one go.  We call array splitting
in the loop in case future optimizations turn indirects into direct
dereferences and we can split more arrays.

Shader-db results on Kaby Lake:

    total instructions in shared programs: 15177605 -> 15177605 (0.00%)
    instructions in affected programs: 0 -> 0
    helped: 0
    HURT: 0

This is unsurprising because nir_lower_vars_to_ssa already effectively
does structure and array splitting internally.  It doesn't actually
split the variables but it's ability to reason about aliasing in the
presence of arrays and structures and pick out scalars or vectors to be
lowered to SSA values is fairly advanced.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand
fa6417495c nir: Add an array splitting pass
This pass looks for array variables where at least one level of the
array is never indirected and splits it into multiple smaller variables.

This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through arrays of arrays and can detect indirects on just
one level or even see that arr[i][0][5] does not alias arr[i][1][j].
This pass exists to help other passes more easily see through arrays of
arrays.  If a back-end does implement arrays using scratch or indirects
on registers, having more smaller arrays is likely to have better memory
efficiency.

v2 (Jason Ekstrand):
 - Better comments and naming (some from Caio)
 - Rework to use one hash map instead of two

v2.1 (Jason Ekstrand):
 - Fix a couple of bugs that were added in the rework including one
   which basically prevented it from running

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand
26eb077ec4 nir: Add a structure splitting pass
This pass doesn't really do much now because nir_lower_vars_to_ssa can
already see through structures and considers them to be "split".  This
pass exists to help other passes more easily see through structure
variables.  If a back-end does implement arrays using scratch or
indirects on registers, having more smaller arrays is likely to have
better memory efficiency.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 21:44:14 -05:00
Jason Ekstrand
b489998e63 nir/types: Add array_or_matrix helpers
Reviewed-by: Thomas Helland<thomashelland90@gmail.com>
2018-08-23 21:44:14 -05:00
Kenneth Graunke
b03dcb1e5f i965: don't include compute resources in "Combined" limits
The combined limits should only include shader stages that can be active
at the same time.  We don't need to include compute.

See also cff290df4c for st/mesa.

Unbreaks i965 from assert failing on driver load since Marek's
45f87a48f9, which dropped the core
Mesa capabilities before adjusting driver limits down to match.
2018-08-23 17:27:27 -07:00
Marek Olšák
9176703788 radeonsi: increase the maximum UBO size to 2 GB
Same as the closed driver.

This causes a failure in GL45-CTS.compute_shader.max, which has a trivial
bug.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
5693ca865d radeonsi: bump MAX_GS_INVOCATIONS
same as the closed driver

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
d3c1b212bc gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZE
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
f6ccd594e7 gallium: add PIPE_CAP_MAX_GS_INVOCATIONS
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
8c71b70f07 tgsi/ureg: don't call tgsi_sanity when it's too slow
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
80aecad0ca st/mesa: fix up uniform limits to be able to expose large UBOs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
cff290df4c st/mesa: don't include compute resources in "Combined" limits
The combined limits should only include shader stages that can be active
at the same time.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
d36af3a9d9 st/mesa: set ctx->Const.SubPixelBits
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
3867af39f9 glsl: fix error checking against MAX_UNIFORM_LOCATIONS
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
f01338118c mesa: make MaxCombinedUniformComponents 64-bit to allow large UBOs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
a8b71f2db8 mesa: add ctx->Const.MaxGeometryShaderInvocations
radeonsi wants to report a different value

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
45f87a48f9 mesa: don't include compute resources in MAX_COMBINED_* limits
5 is the maximum number of shader stages that can be used by 1 execution
call at the same time (e.g. a draw call). The limit ensures that each
stage can use all of its binding points.

Compute is separate and doesn't need the 5x multiplier.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
095515e16c mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES
same number as our closed GL driver

v2: don't use MaxArrayLockSize

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
356ff963ec mesa: remove incorrect change for EXT_disjoint_timer_query
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-08-23 16:56:17 -04:00
Marek Olšák
37eee90df7 glapi: actually implement GL_EXT_robustness for GLES
The extension was exposed but not the functions.

This fixes:
    dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.readn_pixels
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformfv
    dEQP-GLES31.functional.debug.negative_coverage.get_error.state.get_nuniformiv

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-08-23 16:54:30 -04:00
Kenneth Graunke
578e45ab7b intel/decoder: Decode SFIXED values.
This lets us example SAMPLER_STATE's LOD Bias field, among other things.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-08-23 13:04:53 -07:00
Emil Velikov
ae7898dfdb configure: allow building with python3
Pretty much all of the scripts are python2+3 compatible.
Check and allow using python3, while adjusting the PYTHON2 refs.

Note:
 - python3.4 is used as it's the earliest supported version
 - python3 chosen prior to python2

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 17:00:13 +01:00
Eric Engestrom
993a456360 vk/wsi: avoid reading uninitialised memory
It will be ignored by x11_swapchain_result() anyway (because reaching
the `fail` label without setting `result` means the swapchain status was
already a hard error), but the compiler still complains about reading
uninitialised memory.

While at it, drop the unused assignment right before returning.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-23 14:47:59 +01:00
Eric Engestrom
a0f6a11944 egl: drop unused _EGL_BUILT_IN_DRIVER_DRI2
Unused since b174a1ae72 "egl: Simplify the "driver" interface".

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-08-23 14:47:59 +01:00
Samuel Pitoiset
87fbc16e34 radv/gfx9: implement coherent shaders for VK_ACCESS_SHADER_READ_BIT
Single-sample color and single-sample depth (not stencil)
are coherent with shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
2018-08-23 15:42:56 +02:00
Mathieu Bridon
8c8fd0bb8e meson: Run the install script with Python 3
The script was being run directly as an executable, and it has a
Python 2 shebang.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-08-23 12:12:06 +01:00
Emil Velikov
48820ed8da glsl: remove execute bit and shebang from python tests
Just like the rest of the tree - these should be run either as part of
the build system check target, or at the very least with an explicitly
versioned python executable.

Fixes: db8cd8e367 ("glcpp/tests: Convert shell scripts to a python script")
Fixes: 97c28cb082 ("glsl/tests: Convert optimization-test.sh to pure python")
Fixes: 3b52d29227 ("glsl/tests: reimplement warnings-test in python")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-08-23 12:02:45 +01:00
Ian Romanick
c7c0b391ef i965: Enable INTEL_shader_atomic_float_minmax on Gen9+
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
59c17dbc6c i965: Sort Gen9+ extension enables
This is a strictly alphabetic sort, as is done in extensions_table.h
There are other options.  We should pick one and document it.  Right
now, this file is chaos.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
d515c75463 intel/compiler: Implement untyped atomic float min, max, and compare-swap dataport messages
v2: Split changes to the message type field to another patch.  Suggested
by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
f347348f8a intel/compiler: Expand untyped atomic message type field by a bit
This is necessary for a new Gen9 message type that will be added in the
next patch.  There are also Gen8 message types that need the extra bit
(mostly for bindless).

v2: Split off from the next patch.  Suggested by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
d628642a34 intel/compiler: Silence unused parameter warnings
src/intel/compiler/brw_disasm_info.c: In function ‘nir_print_instr’:
src/intel/compiler/brw_disasm_info.c:30:61: warning: unused parameter ‘instr’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                             ^~~~~
src/intel/compiler/brw_disasm_info.c:30:74: warning: unused parameter ‘fp’ [-Wunused-parameter]
 __attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
                                                                          ^~
src/intel/compiler/brw_disasm.c: In function ‘src_ia1’:
src/intel/compiler/brw_disasm.c:850:18: warning: unused parameter ‘_reg_file’ [-Wunused-parameter]
         unsigned _reg_file,
                  ^~~~~~~~~
src/intel/compiler/brw_fs_surface_builder.cpp: In function ‘void brw::surface_access::emit_byte_scattered_write(const brw::fs_builder&, const fs_reg&, const fs_reg&, const fs_reg&, unsigned int, unsigned int, unsigned int, brw_predicate)’:
src/intel/compiler/brw_fs_surface_builder.cpp:193:57: warning: unused parameter ‘size’ [-Wunused-parameter]
                                 unsigned dims, unsigned size,
                                                         ^~~~

v2: Update commit message.  brw_fs_generator.cpp warnings were already
fixed by another patch.  Noticed by Caio.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
0842655ac6 nir: Add floating point atomic min, max, and compare-swap instrinsics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
69ce7baa9e nir: Add floating point atomic add instrinsics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
a390158d10 glsl: Add support for lowering shared-variable float atomics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
39bf3100ac glsl: Add support for lowering SSBO float atomics
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
280ab4afa8 glsl: Add built-in functions for INTEL_shader_atomic_float_minmax
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
c9d52c83a4 mesa: Extension boilerplate for INTEL_shader_atomic_float_minmax
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
88b6c7bc14 glsl: Add built-in functions for NV_shader_atomic_float
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Ian Romanick
9527bb4e70 mesa: Extension boilerplate for NV_shader_atomic_float
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-08-22 20:31:32 -07:00
Gurchetan Singh
c731508b98 meson: fix egl build for android
Haven't tested this, but we do include loader.h
in platform_android.c

Fixes: c5ec155685 ("meson: wire up egl/android")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-08-22 16:47:19 -07:00
Gurchetan Singh
ec6cb01e21 meson: fix egl build for surfaceless
Without this, I get:

 > platform_surfaceless.c:38:10: fatal error: 'loader.h' file not found
 > #include "loader.h"
 >      ^~~~~~~~~~
 > 1 error generated.

Fixes: 108d257a16 ("meson: build libEGL")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

v2: Split up patches, modify commit message (Dylan)
2018-08-22 16:47:09 -07:00
Caio Marcelo de Oliveira Filho
410de0e3f1 nir: Give end_block its own index
Since there's no particular reason for the index to be 0, choose an
index that is not used by other block.  This is convenient when we
store "per-block" data in an array AND look for the successors
data (e.g. any kind of backwards data-flow analysis).

v2: Add a note about end_block's index. (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-22 14:41:26 -07:00
Caio Marcelo de Oliveira Filho
8364ec3fce nir: Skip common instructions when comparing deref paths
Deref paths may share the same deref instructions in their chains,
e.g.

    ssa_100 = deref_var A
    ssa_101 = deref_struct "array_field" of ssa_100
    ssa_102 = deref_array "[1]" of ssa_101
    ssa_103 = deref_struct "field_a" of ssa_102
    ssa_104 = deref_struct "field_a" of ssa_103

when comparing the two last deref instructions, their paths will share
a common sequence ssa_100, ssa_101, ssa_102.  This patch skips to next
iteration if the deref instructions are the same.  Path[0] (the var)
is still handled specially, so in the case above, only ssa_101 and
ssa_102 will be skipped.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-22 14:41:26 -07:00
Caio Marcelo de Oliveira Filho
5196041e93 nir: Export deref comparison functions
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-22 14:41:26 -07:00
Caio Marcelo de Oliveira Filho
7f8ecedced util/dynarray: add a clone function
v2: Fix mem_ctx parameter type. (Thomas)

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-22 14:41:26 -07:00
Mariusz Ceier
61b84b8c14 amd/addrlib: Fix include path for c99_compat.h
Without this patch mesa doesn't compile:

In file included from ../mesa-9999/src/amd/addrlib/addrinterface.cpp:39:
../mesa-9999/src/util/macros.h:29:10: fatal error: c99_compat.h: No such file or directory
 #include "c99_compat.h"
          ^~~~~~~~~~~~~~
compilation terminated.

Fixes: 15ca5ce99a
       ("amd/addrlib: mark returnCode as MAYBE_UNUSED in")
Signed-off-by: Mariusz Ceier <mceier+mesa-dev@gmail.com>
Acked-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-08-22 14:39:02 -07:00
Grazvydas Ignotas
0076ea92a9 vulkan/wsi: fix pointer-integer conversion warnings
For 32bit build. Trivial.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-23 00:34:32 +03:00
Grazvydas Ignotas
9177074524 radv: use different builtin shader cache for 32bit
Currently if 64bit and 32bit programs are used interchangeably, radv
will keep overwriting the cache. Use separate cache files to avoid
that.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-08-23 00:34:32 +03:00