Commit graph

111128 commits

Author SHA1 Message Date
Caio Marcelo de Oliveira Filho
bdaf41107a nir: Add nir_address_format_logical
An address format representing a purely logical addressing model.  In
this model, all deref chains must be complete from the dereference
operation to the variable.  Cast derefs are not allowed.  These
addresses will be 32-bit scalars but the format is immaterial because
you can always chase the chain.  E.g. push constants in anv.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-20 10:53:38 -07:00
Rob Clark
9f61aa3f75 freedreno/a6xx: WFI in program stateobj too
This "fixes" hangs seen w/ various android games.  I think a similar
issue to with constant state, we need to avoid CP_LOAD_STATE until
previous draw completes.

It isn't entirely clear why blob doesn't need to do this, but it might
have a different way to accomplish the same thing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-20 09:10:12 -07:00
Rob Clark
abfb31acdb freedreno/a6xx: make sure binning pass constlen is large enough
Since we use same constant state for both binning pass program state and
draw pass state, and it is possible for binning pass shader to use fewer
consts, we need to make sure we program a large enough constlen.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-20 09:10:12 -07:00
Rob Clark
d200d58e65 freedreno/a6xx: limit IBO state to draw pass
Currently we are only supporting images in FS (and CS) so limit this
stateobj to draw pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-20 09:10:12 -07:00
Rob Clark
54d94f5780 freedreno/a6xx: don't evaluate FS tex state in binning pass
It is unneeded since FS doesn't run in binning pass.

Signed-off-by: Rob Clark <robdclark@chromium.org>
2019-05-20 09:10:12 -07:00
Samuel Pitoiset
daa85a882e radv: decompress FMASK before performing a MSAA decompress using FMASK
This fixes some CTS failures related to VK_EXT_sample_locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-20 12:41:47 +02:00
Dave Airlie
6b2b150a66 nir/validate: fix crash if entry is null.
we validate assert entry just before this, but since that doesn't
stop execution, we need to check entry before the next validation
assert.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-20 16:26:48 +10:00
Qiang Yu
a1d419603f lima/gpir: switch to use nir_lower_viewport_transform
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-20 10:57:11 +08:00
Qiang Yu
a7688b2713 lima/gpir: support vector ssa load
Some vector sysval can't be lowered to scaler, so need to break
it to scaler in nir to gpir convertion.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-20 10:57:11 +08:00
Qiang Yu
4a74e28130 lima/gpir: add helper function for emit load node
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
2019-05-20 10:57:11 +08:00
Timothy Arceri
ac779ff2b7 util: add missing include to build_id.h
Required to use uint8_t

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-05-20 10:24:23 +10:00
Alyssa Rosenzweig
1155446c19 panfrost/midgard: Split up midgard_compile.c (RA)
This commit moves the register allocator out of midgard_compile.c and
into its own midgard_ra.c file. In doing so, a number of dependencies
are identified and moved into their own files in turn. midgard_compile.c
is still fairly monolithic, but this should help.

Code churn, but no functional changes should be introduced by this
commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-19 23:37:45 +00:00
Alyssa Rosenzweig
9cd8cd26de panfrost: Improve fixed-function blending
This fixes a few miscellaneous issues with the fixed-function blending
programming, though it is far from complete. For cases known to be
buggy, we force a fallback to blend shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-19 17:56:35 +00:00
Alyssa Rosenzweig
d1a9b760ea panfrost: Wire up nir_lower_blend
This implements blend shaders via nir_lower_blend, by creating dummy
fragment shaders simply passing through the source color and using the
new lowering pass to inject blendability.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-19 17:56:34 +00:00
Alyssa Rosenzweig
39104221e1 panfrost/midgard: Route new blending intrinsics
To prepare for the new nir_lower_blend pass, we wire up the intrinsics
for tilebuffer reads and constant colour loading.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-19 17:56:14 +00:00
Alyssa Rosenzweig
a1885b2a35 panfrost/nir: Add nir_lower_blend pass
This new lowering pass implements the OpenGL ES blend pipeline in
shaders, applicable to hardware lacking full-featured blending hardware
(including Midgard/Bifrost and vc4). This pass is run on a fragment
shader, rewriting the store to a blended version, loading in the
framebuffer destination color and constant color via intrinsics as
necessary. This pass is sufficient for OpenGL ES 2.0 and is verified to
pass dEQP's blend tests. MIN/MAX modes are included and tested as well.
That said, at present it has the following limitations:

 - MRT is not supported (ES3).
 - sRGB support is missing (ES3).
 - Extended blending is not yet ported from GLSL IR lowering (ES3.2)
 - Dual-source blending is not supported. (N/A)
 - Logic ops are not supported. (N/A)

v2: Fix code conventions (per Ian Romanick's feedback). Implement color
masks.

This pass should be in common nir/ space, but due to non-technical
reasons, for now it's in Panfrost space. In the future, depending if
other drivers need some of the functionality, we can move this back to
src/compiler/nir space.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-19 17:54:56 +00:00
Alyssa Rosenzweig
6b2457e75c panfrost: Fix Bifrost-specific padding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-19 17:41:28 +00:00
Alyssa Rosenzweig
7b5217ad70 panfrost: Cleanup panfrost_job comments
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-19 17:41:26 +00:00
Alyssa Rosenzweig
ae705387a9 panfrost/decode: Decode blend constant
This adds a forgotten decode line on Midgard and adds the field of a
blend constant on Bifrost. The Bifrost encoding is fairly weird; whereas
Midgard is just a regular 32-bit float, Bifrost uses a fancy
fixed-point-esque encoding. The decode logic here is experimentally
correct. The encode logic is a sort of "guesstimate", assuming that the
high byte is just int(f / 255.0) and then solving algebraicly for the
low byte. This might be slightly off in some cases.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-19 17:41:23 +00:00
Alyssa Rosenzweig
3645c781ab panfrost: Hoist blend constant into Midgard-specific struct
This eliminates one major source of #ifdef parity between Midgard and
Bifrost, better representing how the struct acts on Midgard and allowing
proper decodes on Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-19 17:41:21 +00:00
Alyssa Rosenzweig
50382df728 panfrost/decode: Disassemble Bifrost shaders
We already have the Bifrost disassembler in-tree, so now that panwrap is
able to dump Bifrost command streams, hook up the disassembler to
pandecode.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ryan Houdek <Sonicadvance1@gmail.com>
2019-05-19 17:41:08 +00:00
Bas Nieuwenhuizen
4689e98fe8 vulkan/wsi: Set X11 minImageCount to 3.
For IMMEDIATE and FIFO, most games work in a pipelined manner where the
can produce frames at a rate of 1/MAX(CPU duration, GPU duration), but
the render latency is CPU duration + GPU duration.

This means that with scanout from pageflipping we need 3 frames to run
full speed:
1) CPU rendering work
2) GPU rendering work
3) scanout

Once we have a nonblocking acquire that returns a semaphore we can merge
1 and 3. Hence the ideal implementation needs only 2 images, but games
cannot tellwe currently do not have an ideal implementation and that
hence they need to allocate 3 images. So let us do it for them.

This is a tradeoff as it uses more memory than needed for non-fullscreen
and non-performance intensive applications.

Since this is pretty much a TODO that can use the context I added this as
a comment.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-05-19 00:38:03 +00:00
Eric Engestrom
ccb8ea7acf meson: expose glapi through osmesa
Suggested-by: Pierre Guillou <pierre.guillou@lip6.fr>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109659
Fixes: f121a669c7 "meson: build gallium based osmesa"
Fixes: cbbd5bb889 "meson: build classic osmesa"
Cc: Brian Paul <brianp@vmware.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Tested-by: Chuck Atkins <chuck.atkins@kitware.com>
2019-05-18 11:15:04 +01:00
Kenneth Graunke
28c2ce7105 egl: Allow EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY in ES and GL
EGL annoyingly defines a few variants of this token:

   EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_EXT - 0x3138
   EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY_KHR - 0x31BD
   EGL_CONTEXT_OPENGL_RESET_NOTIFICATION_STRATEGY     - 0x31BD

The EGL_EXT_create_context_robustness extension specifies that the EXT
token is only valid for ES contexts, not GL.  The EGL_KHR_create_context
extension defines the KHR version, and says it is only allowed for GL
contexts, and specifically calls out that it's an error for ES contexts.

But EGL 1.5 includes the new suffixless token, which has the same value
as the KHR version, and specifically calls out that it's now valid to
use with both GL and ES contexts.  So we should allow this.

Fixes KHR-NoContext.es32.robustness.no_reset_notification and
KHR-NoContext.es32.robustness.lose_context_on_reset on iris, which
apparently is exposing EGL 1.5.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2019-05-17 15:13:15 -07:00
Jason Ekstrand
1c92358bd8 anv: Only consider minSampleShading when sampleShadingEnable is set
From the Vulkan 1.1.107 spec:

    Sample shading is enabled for a graphics pipeline:

      - If the interface of the fragment shader entry point of the
        graphics pipeline includes an input variable decorated with
        SampleId or SamplePosition. In this case minSampleShadingFactor
        takes the value 1.0.

      - Else if the sampleShadingEnable member of the
        VkPipelineMultisampleStateCreateInfo structure specified when
        creating the graphics pipeline is set to VK_TRUE. In this case
        minSampleShadingFactor takes the value of
        VkPipelineMultisampleStateCreateInfo::minSampleShading.

    Otherwise, sample shading is considered disabled.

In other words, if sampleShadingEnable is set to VK_FALSE, we should
ignore minSampleShading.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-17 20:33:57 +00:00
Jason Ekstrand
8413fd136c anv: Stop forcing bindless for images
This was an unintended artifact of my testing of bindless images.  We
should be choosing bindless or not dynamically.

Fixes: c0d9926df7 "anv: Use bindless handles for images"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-17 19:58:51 +00:00
Neha Bhende
926a6a35cf draw: fix memory leak introduced 7720ce32a
We need to free memory allocation PrimitiveOffsets in draw_gs_destroy().
This fixes memory leak found while running piglit on windows.

Fixes: 7720ce32a ("draw: add support to tgsi paths for geometry streams. (v2)")

Tested with piglit

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-05-17 12:26:48 -06:00
Jason Ekstrand
d2aa65eb18 anv: Emulate texture swizzle in the shader when needed
Now that we have the descriptor buffer mechanism, emulated texture
swizzle can be implemented in a very non-invasive way.  Previous
attempts all tried to extend the push constant based image param
mechanism which was gross.  This could, in theory, be done much faster
with a magic back-end instruction which does indirect MOVs but Vulkan on
IVB is already so slow this isn't going to matter much.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104355
Cc: "19.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-05-17 12:25:58 -05:00
Alyssa Rosenzweig
ea479fdc1d panfrost/midgard: Typofix
Reported-by: Ryan Houdek <Sonicadvance1@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-17 14:59:52 +00:00
Eric Engestrom
6a1f609a4c gitlab-ci: build-test the tools as well
Suggested-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-05-17 11:21:48 +01:00
Samuel Pitoiset
d7501834cd radv: add a workaround for Monster Hunter World and LLVM 7&8
The load/store optimizer pass doesn't handle WaW hazards correctly
and this is the root cause of the reflection issue with Monster
Hunter World. AFAIK, it's the only game that are affected by this
issue.

This is fixed with LLVM r361008, but we need a workaround for older
LLVM versions unfortunately.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-05-17 11:41:19 +02:00
Thomas Hellstrom
47afc5eed7 svga: Add an environment variable to force coherent surface memory
The vmwgfx driver supports emulated coherent surface memory as of version
2.16. Add en environtment variable to enable this functionality for
texture- and buffer maps: SVGA_FORCE_COHERENT.
This environment variable should be used for testing only.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-05-17 08:44:31 +02:00
Thomas Hellstrom
1a66ead1c7 pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flags
In order to be able to add access modes to a pb_validate_entry, update
the pb_validate_add_buffer function to take a pointer hash table and also
to return whether the buffer was already on the validate list.

Update the svga winsys accordingly.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17 08:44:31 +02:00
Thomas Hellstrom
a119da3bc9 svga: Set the rendered-to flag for dma transfers to surfaces
The rendered-to flag indicates that the HW surface content is more recent
than the content of the mob. That's the case after a SurfaceDMA transfer
to the surface.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17 08:44:31 +02:00
Thomas Hellstrom
fb6d09764d winsys/svga: Fix RELOC_INTERNAL mob GPU access
SVGA_RELOC_INTERNAL indicates a transfer between surface and backing mob.
This means that if the GPU for example reads from the surface it writes
to the backing mob. But since the buffer mapping code allows for
simultaneous gpu- and cpu read access, a read from the surface to the mob
will not synchronize a subsequent map to the readback.

Fix this by inverting the mob access mode in a surface relocation with
SVGA_RELOC_INTERNAL set.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17 08:44:31 +02:00
Thomas Hellstrom
eed24156ec svga: Remove the surface_invalidate winsys function
Instead unconditionally call SVGA3D_InvalidateGBSurface() since it's needed
also for Linux for dirty buffers and operation without SurfaceDMA.
For non-guest-backed operation, remove the surface cache surface invalidation
altogether.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2019-05-17 08:44:31 +02:00
Gert Wollny
0f598ed7b3 Revert "softpipe/buffer: load only as many components as the the buffer resource type provides"
This reverts commit 865b9ddae4.

The buffer always reports format PIPE_FORMAT_R8_UNORM so with this patch only
one component would be supported. The original issue is still relevant, but
the fix should be different.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-05-17 08:27:55 +02:00
Dave Airlie
b6e2a9eca7 glsl/nir: init non-static class member.
glsl_to_nir.cpp:276: uninit_member: Non-static class member "sig" is not initialized in this constructor nor in any functions that it calls.

Reported by coverity

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-05-17 12:33:09 +10:00
Dave Airlie
ebdddb36a0 imgui: fix undefined behaviour bitshift.
imgui_draw.cpp:1781: error[shiftTooManyBitsSigned]: Shifting signed 32-bit value by 31 bits is undefined behaviour

Reported by coverity

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-05-17 12:33:09 +10:00
Dave Airlie
2bfe5b8556 glsl: init non-static class member in link uniforms. (v2)
link_uniforms.cpp:477: uninit_member: Non-static class member "shader_storage_blocks_write_access" is not initialized in this constructor nor in any functions that it calls.

Reported by coverity.

v2: fix 9->0 typo (Ilia)

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-05-17 12:33:09 +10:00
Dave Airlie
b2d4d08a5c glsl: init packed in more constructors.
src/compiler/glsl_types.cpp:577: uninit_member: Non-static class member "packed" is not initialized in this constructor nor in any functions that it calls.

from Coverity.

Fixes: 659f333b3a (glsl: add packed for struct types)

Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-05-17 12:33:09 +10:00
Alyssa Rosenzweig
81d3262fa5 panfrost: Cleanup leak todos
Many of these are now patched; one of them we patch here. Regardless,
this is one less thing to worry about in the code, I suppose.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-17 00:14:49 +00:00
Alyssa Rosenzweig
c65271c929 panfrost: assert(0) -> unreachable for some switch
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-05-16 23:42:33 +00:00
Nanley Chery
629806b55b anv: Fix some depth buffer sampling cases on ICL+
Don't attempt sampling with HiZ if the sampler lacks support for it. On
ICL, the HW docs state that sampling with HiZ is not supported and that
instances of AUX_HIZ in the RENDER_SURFACE_STATE object will be
interpreted as AUX_NONE.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2019-05-16 20:54:53 +00:00
Caio Marcelo de Oliveira Filho
ded2c202d5 nir: Only convert SSA values to regs when needed
If the SSA def produced by this instruction is only in the block in
which it is defined and is not used by ifs or phis, then we don't have
a reason to convert it to a register in
nir_lower_ssa_defs_to_regs_block().

The special case for derefs is covered by the general case, so can be
removed: at this point all derefs in the block are
materialized (i.e. the whole deref chain is in the block) and derefs
are not used in phis.

v2: Fix wrong check for if_uses.  If there's such an use, the def is
    not "local_to_block".  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-16 12:23:47 -07:00
Kenneth Graunke
4b5e8eb3c8 st/mesa: Record samplers for extra planes in info->textures_used.
Normally gl_nir_lower_samplers_as_deref records info->textures_used
for us, but this pass runs after that, attempting to assign samplers
in the same order as st_atom_texture's external_samplers_used loop
so the stars align and we get the same locations.

Since we're adding textures late, we need to amend info->textures_used.

iris uses info->textures_used to set up texture bindings; this fixes
Piglit's ext_image_dma_buf_import-sample-{nv12,yuv420,yvu420} there.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-05-16 11:54:07 -07:00
Caio Marcelo de Oliveira Filho
8a995f2b5e nir: Fix nir_opt_idiv_const when negatives are involved
First, allow the case for negative powers of two.  Then ensure that we
use the absolute value of the non-constant value to calculate the
quotient -- this was hinted in the code by the name 'uq'.

This fixes an issue when 'd' is positive and 'n' is negative.  The
ishr will propagate the negative sign and we'll use nir_ineg() again,
incorrectly.

v2: First version used only ishr, but that isn't sufficient, since it
    never can produce a zero as a result.  (Jason)
    Allow negative powers of two.  (Caio)

Fixes: 74492ebad9 "nir: Add a pass for lowering integer division by constants"
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-05-16 10:55:03 -07:00
Eric Anholt
ef88e23d03 freedreno: Log the number of loops in the shader for shader-db.
shader-db's report.py will use this to see when we've changed loop
unrolling behavior on a shader and skip including other stats like
instruction count from being considered for that shader, since they won't
be useful as a proxy for real world performance in that case.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eduardo Lima Mitev <elima@igalia.com>
2019-05-16 10:25:22 -07:00
Eric Anholt
c2e68bebb4 freedreno: Output the same shader-db format as v3d and intel.
This lets us reuse their report.py, at the expense of fd-report.py no
longer working.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eduardo Lima Mitev <elima@igalia.com>
2019-05-16 10:25:20 -07:00
Eric Anholt
6d9b45171d freedreno: Remove the ir3_tgsi_to_nir() helper function.
It was more of a hindrance, as it pretended that we could compile in the
driver with a missing screen.

Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Eduardo Lima Mitev <elima@igalia.com>
2019-05-16 10:25:18 -07:00