Commit graph

74909 commits

Author SHA1 Message Date
Dave Airlie
bd71f3e4fe r600: fix masks for two of the unused evergreen regs.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-07 09:58:58 +10:00
Edward O'Callaghan
d108b69d2c gallium: Remove redundant NULL ptr checks
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:23 +01:00
Edward O'Callaghan
13eb5f596b gallium/drivers: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:23 +01:00
Edward O'Callaghan
150c289f60 gallium/auxiliary: Sanitize NULL checks into canonical form
Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:23 +01:00
Edward O'Callaghan
147fd00bb3 gallium/auxiliary: Trivial code style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:22 +01:00
Edward O'Callaghan
25b3d554c4 gallium/drivers: Trivial code-style cleanup
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:22 +01:00
Edward O'Callaghan
34782eec31 gallium/auxiliary: Fix zero integer literal to pointer comparison
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:02 +01:00
Edward O'Callaghan
3edae10601 winsys/amdgpu: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:09:54 +01:00
Edward O'Callaghan
82871081fc svga: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:09:52 +01:00
Edward O'Callaghan
70d2d3ef7f llvmpipe: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:09:47 +01:00
Edward O'Callaghan
be51020f2a gallium/drivers/nouveau: Make use of ARRAY_SIZE macro
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:03:17 +01:00
Edward O'Callaghan
7e43a28079 gallium/radeon*: Remove useless casts
These are unnecessary and are likely just left overs from prior
work.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 11:52:16 +01:00
Ilia Mirkin
0ef5c8ab74 nv50/ir: fold shl + mul with immediates
On SM20 this gives:

total instructions in shared programs : 6299222 -> 6294240 (-0.08%)
total gprs used in shared programs    : 944139 -> 944068 (-0.01%)
total local used in shared programs   : 54116 -> 54116 (0.00%)

                local        gpr       inst      bytes
    helped           0         126        2781        2781
      hurt           0          55          11          11

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-05 18:56:43 -05:00
Ilia Mirkin
abd326e81b nv50/ir: propagate indirect loads into instructions
This way $r1 = $r0 + 4; c1[$r1] becomes c1[$r0+4].

On SM35:

total instructions in shared programs : 6206257 -> 6185058 (-0.34%)
total gprs used in shared programs    : 911045 -> 910722 (-0.04%)
total local used in shared programs   : 39072 -> 39072 (0.00%)

                local        gpr       inst      bytes
    helped           0         417        4195        4195
      hurt           0         280           0           0

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-05 17:50:23 -05:00
Ilia Mirkin
31fde8faba nv50/ir: flip shl(add, imm) into add(shl, imm)
This works when the add also has an immediate. This often happens in
address calculations. These addresses can then be inlined as well.

On code targeted to SM35:

total instructions in shared programs : 6223346 -> 6206257 (-0.27%)
total gprs used in shared programs    : 911075 -> 911045 (-0.00%)
total local used in shared programs   : 39072 -> 39072 (0.00%)

                local        gpr       inst      bytes
    helped           0         119        3664        3664
      hurt           0          74          15          15

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-05 17:50:23 -05:00
Eric Anholt
a4eff86f4a vc4: Fix accidental scissoring when scissor is disabled.
Even if the rasterizer has scissor disabled, we'll have whatever
vc4->scissor bounds were last set when someone set up a scissor, so we
shouldn't clip to them in that case.

Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
2015-12-05 13:12:27 -08:00
Eric Anholt
d16d666776 vc4: Disable RCL blitting when scissors are enabled.
We could potentially handle scissored blits when they're tile aligned, but
it doesn't seem worth it.  If you're doing a scissored blit, you're
probably a testcase.

Fixes piglit's fbo-scissor-blit fbo
2015-12-05 13:12:27 -08:00
Eric Anholt
0afe83078d vc4: Bring over cleanups from submitting to the kernel. 2015-12-05 13:12:27 -08:00
Samuel Pitoiset
9f6ff76fdc nvc0: expose a group of performance metrics for SM30 (Kepler)
This allows to monitor these performance metrics through
GL_AMD_performance_monitor.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
0afd8f7bd7 nvc0: re-introduce performance metrics for SM30 (Kepler)
This implements more performance metrics than the previous support,
but some other metrics still need to be figured out.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
af275b8839 nvc0: remove useless counting operations for MP counters
Those bits were related to old performance metrics support.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
6667355d4b nvc0: remove old performance metrics support on Kepler
These performance metrics will be re-introduced in an upcoming
patch that will follow the same design as Fermi.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
662eb434ee nvc0: remove wrong inst_issued HW SM perf counter on Kepler
inst_issued is performance metric not a hardware event on Kepler (SM30).
It will be re-introduced in an upcoming patch.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
342ea31193 nvc0: add missing HW SM perf counters for SM30 (Kepler)
SM30 is the compute capability version for GK104/GK106/GK107.
This also introduces a new signal group selection called UNK0F.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Samuel Pitoiset
7f42688017 nvc0: fix the comment that describe MP counters storage on Kepler
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-05 19:23:34 +01:00
Rob Clark
58efff89a2 freedreno/ir3: nir shader prints with 'disasm' debug option
Move these to 'disasm' instead of the more verbose 'optmsgs' since, like
the tgsi dumps, it is useful without the more verbose compiler logging
enabled.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-05 08:48:19 -05:00
Ilia Mirkin
a3f90ef0a6 gallium/util: fix pipe_debug_message macro to allow 0 args
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
2015-12-04 15:24:17 -05:00
Eric Anholt
a69ac4e89c vc4: Add debug dumping of MSAA surfaces. 2015-12-04 09:24:36 -08:00
Eric Anholt
3c3b1184eb vc4: Add support for laying out MSAA resources.
For MSAA, we store full resolution tile buffer contents, which have their
own tiling format.  Since they're full resolution buffers, we have to
align their size to full tiles.
2015-12-04 09:24:36 -08:00
Eric Anholt
74c4b3b80c vc4: Add support for storing sample mask.
From the API perspective, writing 1 bits can't turn on pixels that were
off, so we AND it with the sample mask from the payload.
2015-12-04 09:23:55 -08:00
Eric Anholt
3a508a0d94 vc4: Fix up tile alignment checks for blitting using just an RCL.
We were checking that the blit started at 0 and was 1:1, but not that it
went to the full width of the surface, or that the width was aligned to a
tile.  We then told it to blit to the full width/height of the surface,
causing contents to be stomped in a bunch of MSAA tests that happen to
include half-screen-width blits to 0,0.
2015-12-04 09:10:53 -08:00
Eric Anholt
a664233042 vc4: Add support for loading sample mask. 2015-12-04 09:10:53 -08:00
Rob Clark
4b18d51756 freedreno/ir3: convert scheduler back to recursive algo
I've played with a few different approaches to tweak instruction
priority according to how much they increase/decrease register pressure,
etc.  But nothing seems to change the fact that compared to original
(pre-multiple-block-support) scheduler, in some edge cases we are
generating shaders w/ 5-6x higher register usage.

The problem is that the priority queue approach completely looses the
dependency between instructions, and ends up scheduling all paths at the
same time.

Original reason for switching was that recursive approach relied on
starting from the shader outputs array.  But we can achieve more or less
the same thing by starting from the depth-sorted list.

shader-db results:

total instructions in shared programs:          113350 -> 105183 (-7.21%)
total dwords in shared programs:                219328 -> 211168 (-3.72%)
total full registers used in shared programs:   7911 -> 7383 (-6.67%)
total half registers used in shader programs:   109 -> 109 (0.00%)
total const registers used in shared programs:  21294 -> 21294 (0.00%)

                 half       full      const      instr     dwords
    helped           0         322           0         711         215
      hurt           0         163           0          38           4

The shaders hurt tend to gain a register or two.  While there are also a
lot of helped shaders that only loose a register or two, the more
complex ones tend to loose significanly more registers used.  In some
more extreme cases, like glsl-fs-convolution-1.shader_test it is more
like 7 vs 34 registers!

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-04 10:27:09 -05:00
Rob Clark
ad2cc7bddc freedreno/ir3: don't reuse a0.x across blocks
It causes confusion in sched if we need to split_addr() since otherwise
we wouldn't easily know which block the new addr instr will be scheduled
in.  So just side-step the whole situation.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-04 10:27:09 -05:00
Rob Clark
8e52344dc1 freedreno/ir3: rename ir3_block::bd
We'll need to add similar for ir3_instruction, but following the pattern
to use 'id' seems confusing.  Let's just go w/ generic 'data' as the
name.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-04 10:27:09 -05:00
Giuseppe Bilotta
d566382a98 util: fix comment typo
Undefining the NDEBUG is relevant for release build, as they are the
ones that set it.

[Emil Velikov: split from previous patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-04 14:06:41 +00:00
Giuseppe Bilotta
efaac624af xvmc: force assertion in XvMC tests
This follows the src/util/u_atomic_test.c model of undefining NDEBUG
unconditionally throughouth the XvMC tests, to force asserts regardless
of debug mode.

The comment on u_atomic_test.c is also fixed (read 'debug' where it
should have been 'release').

v2: s/debug/release/ in relevant comments

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
[Emil Velikov: keep the src/util/ hunk as separate patch]
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-04 14:06:41 +00:00
Giuseppe Bilotta
4839353634 radeon: const correctness
Add missing `const` specifier for pointer pointing to a const struct.

Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-04 14:06:41 +00:00
Giuseppe Bilotta
d61802b5e0 radeon: whitespace cleanup
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-12-04 14:06:38 +00:00
Emil Velikov
1074e38fbb mesa/tests: add KHR_debug GLES glGetPointervKHR entry points
Should have been part of commit f53f9eb8d4 "glapi: add GetPointervKHR
to the ES dispatch".

v2: comment out the ES1.1 symbol and use the same description (pattern)
as elsewhere (Matt)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93235
Fixes: f53f9eb8d4 "glapi: add GetPointervKHR to the ES dispatch".
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org> (v1)
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-04 13:56:43 +00:00
Jason Ekstrand
b715e6d528 i965/vec4: Stop pretending to support indirect output stores
Since we're using nir_lower_outputs_to_temporaries to shadow all our
outputs, it's impossible to actually get an indirect store.  The code we
had to "handle" this was pretty bogus as it created a register with a
reladdr and then stuffed it in a fixed varying slot without so much as a
MOV.  Not only does this not do the MOV, it also puts the indirect on the
wrong side of the transaction.  Let's just delete the broken dead code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-03 20:58:12 -08:00
Jason Ekstrand
aa35b0c2c7 i965/vec4: Get rid of the nir_inputs array
It's not really buying us anything at this point.  It's just a way of
remapping one offset namespace onto another.  We can just use the location
namespace the whole way through.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-03 20:58:12 -08:00
Jason Ekstrand
c6bcc23369 nir/lower_io: Pass the builder and type_size into get_io_offset
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-03 20:58:12 -08:00
Ilia Mirkin
204f803ce0 nv50/ir: replace zeros in movs as well
The original change to put zeroes directly into instructions created
conditional mov's with the zero immediate. However that can't be
emitted, so make sure to replace the zero with r63.

Fixes: 52a800a68 (nv50/ir: allow immediate 0 to be loaded anywhere)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-03 23:46:02 -05:00
Ilia Mirkin
a3722b81f5 nv50/ir: fold fma/mad when all 3 args are immediates
This happens pretty rarely, but might as well do it when it does.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-03 23:02:57 -05:00
Ilia Mirkin
2b98914fe0 nv50/ir: avoid looking at uninitialized srcMods entries
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-03 23:02:57 -05:00
Ilia Mirkin
49692f86a1 nv50/ir: fix DCE to not generate 96-bit loads
A situation where there's a 128-bit load where the last component gets
DCE'd causes a 96-bit load to be generated, which no GPU can actually
emit. Avoid generating such instructions by scaling back to 64-bit on
the first load when splitting.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-03 23:02:57 -05:00
Roland Scheidegger
51140f452a draw: fix clipping of layer/vp index outputs
This was just plain broken. It used always the value from v0 (for vp_index)
but would pass the value from the provoking vertex to later stages - but only
if there was a corresponding fs input, otherwise the layer/vp index would get
lost completely (as it would try to interpolate the (unsigned) values as
floats).
So, make it obey provoking vertex rules (drivers relying on draw will need to
do the same). And make sure that the default interpolation mode (when no
corresponding fs input is found) for them is constant.
Also, change the code a bit so constant inputs aren't interpolated then
copied over later.

Fixes the new piglit test gl-layer-render-clipped.

v2: more consistent whitespaces fixes for function defs, and more tab killing
(overall still not quite right however).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-04 03:42:19 +01:00
Roland Scheidegger
5ea5b169e9 softpipe: use provoking vertex for layer
Same as for llvmpipe, albeit softpipe only really handles multiple layers,
not multiple viewports/scissors.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-04 03:42:19 +01:00
Roland Scheidegger
ddaf8d7b10 llvmpipe: use provoking vertex for layer/viewport
d3d10 actually requires using provoking (first) vertex. GL is happy with
any vertex (as long as we say it's undefined in the corresponding queries).
Up to now we actually used vertex 0 for viewport index, and vertex 1 for
layer (for tris), which really didn't make sense (probably a typo). Also,$
since we reorder vertices of clockwise triangle, that actually meant we used
a different vertex depending if the traingle was cw or ccw (still ok by gl).
However, it should be consistent with what draw (clip) does, and using
provoking vertex seems like the sensible choice (draw clip will be fixed
next as it is totally broken there).
While here, also use the correct viewport always even when not needed
in setup (we pass it down to jit fragment shader it might be needed there
for getting correct near/far depth values).

No piglit changes.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-04 03:42:19 +01:00