Commit graph

52286 commits

Author SHA1 Message Date
Eric Anholt
bbdc83bca9 intel: Add a batch flush between front-buffer downsample and X protocol.
This was already happening because blorp happens to flush at the end of
every call, but we have been talking about removing that at some point,
and this would surely get overlooked.

v2 (Kenneth Graunke): Rebase on latest master.  Note that we did remove
   the other flush, and this change actually did get overlooked!

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-30 11:30:44 -07:00
Eric Anholt
6404fcb266 i965: Directly call intel_batchbuffer_flush() after i915 split.
intel_flush() now did nothing except call through (and
intel_batchbuffer_flush() does the no-op check, too!)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-30 11:30:44 -07:00
Eric Anholt
09e2df5961 i965/vs: Fix regression on pre-gen6 with no VS uniforms in use.
df06745c5a made it so that we didn't
allocate extra uniform space for unused clip planes, which also
incidentally made us not allocate any space at all, which we were relying
on for this no-uniforms case.  Instead of putting the knowledge of this
special HW exception into the thing that normally preallocates prog_data
for us, just allocate it here.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68766
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-08-30 11:29:50 -07:00
Vadim Girlin
f7217b99f2 r600g: enable SB backend by default
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-08-30 15:51:11 +04:00
Vadim Girlin
29ff2e907d r600g: fix color exports when we have no CBs
We need to export at least one color if the shader writes it,
even when nr_cbufs==0.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2013-08-30 15:51:11 +04:00
Vinson Lee
74be77a99e nvc0/ir: Initialize NVC0LegalizePostRA member variables.
Fixes "Uninitialized pointer field" defects reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-08-29 20:42:24 -07:00
Roland Scheidegger
a479f34025 gallivm: support per-pixel min/mag filter in SoA path
Since we can have per-pixel lod we should also honor the filter per-pixel
(in fact we didn't honor it per quad neither in the multiple quad case).
Do this by running the linear path and simply beating the weights into shape
(the sample with the higher weight is the one which should have been chosen
with nearest filtering hence adjust filter weight to 1.0/0.0 based on that).
If all pixels use nearest filter (either min and mag) then still run just a
nearest filter as this is way cheaper (probably around 4 times faster for 2d,
more for 3d case) and it should be relatively rare that pixels really need
different filtering. OTOH if all pixels would require linear don't do anything
special since the linear path with filter adjustments shouldn't really be all
that much more expensive than ordinary linear, and we think it's rare that
min/mag filters are configured differently so there doesn't seem much value
in trying to optimize this further.
This does not yet fix the AoS path (though currently AoS is only used for
single quads hence it could be considered less broken, just never honoring
per-pixel filter decision but doing it per quad).

v2: simplify code a bit (unify min linear and min nearest cases)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-08-30 02:16:45 +02:00
Roland Scheidegger
81cfcdbd87 gallivm: don't calculate square root of rho if we use accurate rho method
While a sqrt here and there shouldn't hurt much (depending on the cpu) it is
possible to completely omit it since rho is only used for calculating lod and
there log2(x) == 0.5*log2(x^2). Depending on the exact path taken for
calculating lod this means we get a simple mul instead of sqrt (in case of
nearest mip filter in fact we don't need to replace the sqrt with something
else at all), only in some not very useful path this doesn't work (combined
brilinear calculation of int level and fractional lod, accurate rho calc but
brilinear filtering seems odd).
Apart from being faster as an added bonus this should increase our crappy
fractional accuracy of lod, since fast_log2 is only good for ~3bits and this
should increase accuracy by one bit (though not used if dimension is just one
as we'd need an extra mul there as we never had the squared rho in the first
place).

v2: use separate ilog2_sqrt function if we have squared rho.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-08-30 02:16:45 +02:00
Roland Scheidegger
10e40ad11d gallivm: refactor num_lods handling
This is just preparation for per-pixel (or per-quad in case of multiple quads)
min/mag filter since some assumptions about number of miplevels being equal
to number of lods no longer holds true.
This change does not change behavior yet (though theoretically when forcing
per-element path it might be slower with different min/mag filter since the
code will respect this setting even when there's no mip maps now in this case,
so some lod calcs will be done per-element just ultimately still the same
filter used for all pixels).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-08-30 02:16:45 +02:00
Vinson Lee
4a6d2f3dd7 radeonsi: Early return if no depth or stencil on release builds.
Fixes "Missing break in switch" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2013-08-29 15:49:12 -07:00
Rob Clark
de10d383d0 freedreno: pipe loader for either kgsl or msm
The downstream android kernel driver is "kgsl", the upstream drm/kms
driver is called "msm".  Since libdrm_freedreno handles the differences
between the two, we need to load the same thing for either device.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-29 17:35:05 -04:00
Rob Clark
e95b7d89b9 freedreno: updates for msm drm/kms driver
There where some small API tweaks in libdrm_freedreno to enable support
for msm drm/kms driver.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-29 17:35:05 -04:00
Rob Clark
0267f264cc freedreno/a3xx/compiler: handle sync flags better
We need to set the flag on all the .xyzw components that are written by
the instruction, not just on .x.  Otherwise a later use of rN.y (for
example) will not trigger the appropriate sync bit to be set.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-29 17:35:04 -04:00
Rob Clark
4a2b5b2384 freedreno/a3xx/compiler: better const handling
Seems like most/all instructions have some restrictions about const src
registers.  In seems like the 2 src (cat2) instructions can take at most
one const, and the 3 src (cat3) instructions can take at most one const
in the first 2 arguments.  And so on.  Handle this properly now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-29 17:35:04 -04:00
Anuj Phogat
9c0b7be964 glsl: Allow precision qualifiers for sampler types
GLSL 1.30 doesn't allow precision qualifiers on sampler types,
but in GLSL ES, sampler types are also allowed. This seems like
an oversight (since the intention of including these in GLSL 1.30
is to allow compatibility with ES shaders).

Currently, Mesa allows "default" precision qualifiers to be set for
sampler types in GLSL (commit d5948f2). This patch makes it follow
GLSL ES rules and also allow declaring sampler variables with a
precision qualifier in GLSL 1.30 (and later). e.g.
uniform lowp sampler2D sampler;

This fixes a shader compilation error in Khronos OpenGL conformance
test "depth_texture_mipmap".

V2: Update comments.
Signed-off-by: Ian Romanick <idr@lists.freedesktop.org>

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <idr@lists.freedesktop.org>
Cc: <mesa-stable@lists.freedesktop.org>
2013-08-29 12:10:57 -07:00
Matt Turner
1ecfdba98a glsl: Add heuristics to print floating-point numbers better.
v2: Fix *.expected files to match.
Reviewed-by: Paul Berry <strereotype441@gmail.com>
2013-08-29 12:07:28 -07:00
Jonathan Gray
57cf5946ce radeonsi: Make sure libdrm_radeon headers are picked up from the right place
And remove libdrm/ from a winsys include statement.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
2013-08-29 15:37:44 +02:00
Brian Paul
4e7f1346ae draw: fix point/line/triangle determination in draw_need_pipeline()
The previous point/line/triangle() functions didn't handle GS primitives.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-08-29 07:29:31 -06:00
Christian König
aebd065a64 radeon/uvd: fix MPEG2/4 ref frame index limit
Otherwise the first few frames have an incorrect reference index.

Signed-off-by: Christian König <christian.koenig@amd.com>
2013-08-29 08:51:12 +02:00
Vinson Lee
57684d52e9 nouveau: Copy m4x4 and m8x8 separately.
Silences Coverity "Out-of-bounds access" defect.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2013-08-28 23:23:49 -07:00
Kenneth Graunke
df06745c5a i965: Allocate just enough space for user clip planes in uniform arrays.
Previously, we allocated space in brw_vs_prog_data's params and
pull_params arrays for MAX_CLIP_PLANES vec4s---even when it wasn't
necessary.

On a 64-bit architecture, this used 0.5 kB of space (8 clip planes *
4 floats per plane * 8 bytes per float pointer * 2 arrays of pointers =
512 bytes).  Since this cost was per-vertex shader, it added up.

Conveniently, we already store the number of clip plane constants in the
program key.  By using that, we can allocate the exact amount of space
needed.  For the common case where user clipping is disabled, this means
0 bytes.

While we're here, mention exactly what code requires this extra space,
since it wasn't obvious.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-28 14:12:48 -07:00
Chad Versace
72b3c6c96f i965: Silence unused variable warning in release build
Use `(void) success;` to silence this warning:

  i965/brw_vs.c:481:12:
  warning: unused variable 'success' [-Wunused-variable]
         bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram,

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2013-08-28 10:42:51 -07:00
Fabian Bieler
cd18269705 mesa/main: Check for 0 size draws after validation.
When validating draw parameters move check for 0 draw count last
(drawing with count 0 is not an error), so that other parameters (e.g.: the
primitive type) are validated and the correct errors (if applicable) are
generated.

>From the OpenGL 3.3 spec page 33 (page 48 of the PDF):
"[Regarding DrawArraysOneInstance, in terms of which other draw operations
are defined:]
If count is negative, an INVALID_VALUE error is generated."

This patch also changes the bahavior of MultiDrawElements to perform the draw
operation if some primitive's index counts are zero.

Signed-off-by: Fabian Bieler <fabianbieler@fastmail.fm>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-27 15:11:52 -07:00
Matt Turner
ac74de3710 glsl: Add built-ins from ARB_shader_bit_encoding to ARB_gpu_shader5.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-27 15:06:16 -07:00
Matt Turner
4929be0b5f i965/vs: Add support for translating ir_triop_fma into MAD.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-27 15:03:30 -07:00
Matt Turner
530842127e i965/fs: Add support for translating ir_triop_fma into MAD.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-27 15:03:30 -07:00
Matt Turner
e817b94a2c i965/fs: Assert that ir_expressions are usable by 3-src instructions.
MAD will be generated directly from ir_triop_fma, so this assertion
checks that all ir_expressions are usable.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-27 15:03:30 -07:00
Matt Turner
d55c543c36 glsl: Add support for new fma built-in in ARB_gpu_shader5.
v2: Add constant folding support.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-27 15:03:30 -07:00
Matt Turner
6829c18609 glsl: Add new fma built-in IR and prototype from ARB_gpu_shader5.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-27 15:03:30 -07:00
Marek Olšák
adb93e3bda r300g: enable MSAA on r300-r400, be careful about using color compression
MSAA was tested by one user on RS690 and it works for him with color
compression (CMASK) disabled. Our theory is that his chipset lacks CMASK RAM.

Since we don't have hardware documentation about which chipsets actually have
CMASK RAM, I had to take a guess based on the presence of HiZ.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-27 23:18:54 +02:00
Roland Scheidegger
bd3909f265 draw: clean up setting stream out information a bit
In particular noone is interested in the vertex count, so drop that,
and also drop the duplicated num_primitives_generated /
so.primitives_storage_needed variables in drivers. I am unable for now to figure
out if primitives_storage_needed in SO stats (used for d3d10) should
increase if SO is disabled, though the equivalent num_primitives_generated
used for OpenGL definitely should increase. In any case we were only counting
when SO is active both in softpipe and llvmpipe anyway so don't pretend there's
an independent num_primitives_generated counter which would count always.
(This means the PIPE_QUERY_PRIMITIVES_GENERATED count will still be wrong just
as before, should eventually fix this by doing either separate counting for this
query or adjust the code so it always counts this even if SO is inactive depending
on what's correct for d3d10.)

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-08-27 16:59:39 +02:00
Roland Scheidegger
aff2ecf09a llvmpipe: support nested/overlapping queries for all query types
There's just no way resetting the counters is working with nested/overlapping
queries.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-08-27 16:59:01 +02:00
Roland Scheidegger
4900e625bd softpipe: support nested/overlapping queries for all query types
There's just no way resetting the counters is working with nested/overlapping
queries.

Reviewed-by: Brian Paul <brianp@vmware.com>
2013-08-27 16:58:20 +02:00
Matt Turner
d8ac987f6a glsl: Disallow uniform block layout qualifiers on non-uniform block vars.
Cc: 9.2 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68460
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-26 23:19:14 -07:00
Ian Romanick
d127a0343d i915: Optimize SEQ and SNE when two operands are uniforms
SEQ and SNE are not native i915 instructions, so they each generate at
least 3 instructions.  If both operands are uniforms or constants, we
get 5 instructions like:

                U[1] = MOV CONST[1]
                U[0].xyz = SGE CONST[0].xxxx, U[1]
                U[1] = MOV CONST[1].-x-y-z-w
                R[0].xyz = SGE CONST[0].-x-x-x-x, U[1]
                R[0].xyz = MUL R[0], U[0]

This code is stupid.  Instead of having the individual calls to
i915_emit_arith generate the moves to utemps, do it in the caller.  This
results in code like:

                U[1] = MOV CONST[1]
                U[0].xyz = SGE CONST[0].xxxx, U[1]
                R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w
                R[0].xyz = MUL R[0], U[0]

This allows fs-temp-array-mat2-index-col-wr and
fs-temp-array-mat2-index-row-wr to fit in hardware limits (instead of
falling back to software rasterization).

NOTE: Without pending patches to the piglit tests, these tests will now
fail.  This is an unrelated, pre-existing issue.

v2: Copy most of the body of the commit message into comments in the
code.  Suggested by Eric.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-08-26 22:11:26 -07:00
Tom Stellard
f3e86d4a68 clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
CC: "9.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2013-08-26 18:27:03 -07:00
Niels Ole Salscheider
ef6ed7220a st/clover: Add event to deps even if it has been triggered
The command is submitted once the event has been triggered, but it might not
have completed yet. Therefore, we have to add it to deps in order to wait on it.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2013-08-26 18:25:17 -07:00
Niels Ole Salscheider
4a3505d548 st/clover: Profiling support
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Acked-by: Francisco Jerez <currojerez@riseup.net>
2013-08-26 18:25:17 -07:00
Dave Airlie
4763a032a0 tgsi_build: fix order of arguments for ind register build
This was broken when arrayid was added.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-27 10:41:27 +10:00
Dave Airlie
81204d0e9c tgsi: finish declaration parsing for arrays.
I previously fixed this partly in 9e8400f4c9,
however I didn't go far enough in testing it, now when I parse a TGSI shader
with arrays in it my iterator can see the ArrayID set to the proper value.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-27 10:41:09 +10:00
Brian Paul
92cbfded6a svga: replace 0 with PIPE_OK in a few places 2013-08-26 15:49:16 -06:00
Brian Paul
5e7ac28ebf swrast: init i0, i1 values to silence warnings
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-08-26 12:52:06 -06:00
Brian Paul
ef47ab520d mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT()
to silence gcc 4.8.1 warnings.  And improve the ASSERT(0) call.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-08-26 12:52:06 -06:00
Brian Paul
f91f6ef739 glsl: init limit=0 to silence uninitialized var warning
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-26 12:52:06 -06:00
Kenneth Graunke
d65e3c082a i965/vs: Allocate register set once at context creation.
Now that we use a fixed set of register classes, we can set up the
register set and conflict graphs once, at context creation, rather than
on every VS compile.  This is obviously less expensive, and also what
we already do in the FS backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-26 11:21:10 -07:00
Kenneth Graunke
a149f744d9 i965/vs: Move base_reg_count computation to brw_alloc_reg_set().
We're soon going to be calling brw_alloc_reg_set() from outside of the
visitor, where we don't have the precomputed "max_grf" variable handy.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-26 11:21:10 -07:00
Kenneth Graunke
7aaaa8bc8f i965/vs: Expose the payload registers to the register allocator.
For now, nothing else can get allocated over them.  That may change at
some point in the future.

This also means that base_reg_count can be computed without knowing the
number of registers used for the payload, which is required if we want
to allocate the register set once at context creation time.

See commit 551e1cd44f, which implemented
virtually identical code in the FS backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-26 11:21:10 -07:00
Kenneth Graunke
528d70d0b5 i965/vs: Use a fixed set of register classes.
Arrays, structures, and matrices use large VGRFs of arbitrary sizes.
However, split_virtual_grfs() breaks those down into VGRFs of size 1.

For reference, commit 5d90b98879 is the
analogous change to the FS backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-08-26 11:21:10 -07:00
Paul Berry
cfe39ea14e i965: Allow C++ type safety in the use of enum brw_urb_write_flags.
(From a suggestion by Francisco Jerez)

If an enum represents a bitfield of flags, e.g.:

enum E {
  A = 1,
  B = 2,
  C = 4,
  D = 8,
};

then C++ normally prohibits statements like this:

enum E x = A | B;

because A and B are implicitly converted to ints before OR-ing them,
and an int can't be stored in an enum without a type cast.  C, on the
other hand, allows an int to be implicitly converted to an enum
without casting.

In the past we've dealt with this situation by storing flag bitfields
as ints.  This avoids ugly casting at the expense of some type safety
that C++ would normally have offered (e.g. we get no warning if we
accidentally use the wrong enum type).

However, we can get the best of both worlds if we override the |
operator.  The ugly casting is confined to the operator overload, and
we still get the benefit of C++ making sure we don't use the wrong
enum type.

v2: Remove unnecessary comment and unnecessary use of "enum" keyword.
Use static_cast.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2013-08-26 10:15:51 -07:00
Paul Berry
612226c43b i965: Remove redundant (and uninitialized) field vec4_generator::ctx.
We never noticed that this field was uninitialized because it is only
used in an error path that reports internal Mesa errors.

But it's silly to have it around anyway because &brw->ctx is
equivalent.

Should fix Coverity defect CID 1063351: Uninitialized pointer field
(UNINIT_CTOR) /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp: 148

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-08-26 08:55:39 -07:00