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i965/vs: Add support for translating ir_triop_fma into MAD.

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Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
This commit is contained in:
Matt Turner 2013-08-02 10:28:16 -07:00
parent 530842127e
commit 4929be0b5f
2 changed files with 12 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_vec4.h
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@ -440,6 +440,7 @@ public:
vec4_instruction *FBH(dst_reg dst, src_reg value);
vec4_instruction *FBL(dst_reg dst, src_reg value);
vec4_instruction *CBIT(dst_reg dst, src_reg value);
vec4_instruction *MAD(dst_reg dst, src_reg c, src_reg b, src_reg a);
int implied_mrf_writes(vec4_instruction *inst);

11
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -144,6 +144,7 @@ ALU3(BFI2)
ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
ALU3(MAD)
/** Gen4 predicated IF. */
vec4_instruction *
@ -1711,6 +1712,16 @@ vec4_visitor::visit(ir_expression *ir)
assert(!"should have been lowered by vec_index_to_cond_assign");
break;
case ir_triop_fma:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);
op[2] = fix_3src_operand(op[2]);
/* Note that the instruction's argument order is reversed from GLSL
* and the IR.
*/
emit(MAD(result_dst, op[2], op[1], op[0]));
break;
case ir_triop_lrp:
op[0] = fix_3src_operand(op[0]);
op[1] = fix_3src_operand(op[1]);