On DG2 the HW will fetch the binding entries into the cache
for every single thread when a compute walker is dispatched,
wiping out the advantages of the cache prefetch.
The spec also advises to not do a cache prefetch when we have more than
31 binding table entries, but most real world applications will never
hit that limit.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18498>
For fast-linking, we really want to upload the binaries directly in
a library to avoid creating and uploading at pipeline creation time.
To achieve that, add a radeon_winsys_bo pointer to radv_shader in
order to indicate that a shader is already uploaded. When a lib is
imported, the pipeline slab BO is also incremented to make sure it's
not freed when the lib is destroyed.
This also allows to free binaries right after they are uploaded.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18860>
dynamic rasterization samples got added late, and I forgot to update this
Fixes: 1deb83fb86 ("vulkan: Add more dynamic multisample states")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18896>
Sometimes we only access a subset of a texture's miplevels, for example
when peforming GenerateMipmaps(). We want to be able to look for the
aux state being ISL_AUX_STATE_PASS_THROUGH for only the relevant
miplevels, rather than all of them, when deciding whether to bypass aux.
Avoids another occurrence of issues with reading via aux while in
passthrough state (see issue #6558), fixing misrendering in Chrome
and Electron apps while resizing the window to be smaller (#7272).
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7272
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19028>
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
To clean up compilation warnings about unused variables
when asserts are disabled.
v2: UNUSED -> ASSERTED (Eric Engestrom)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19016>
Otherwise the wrong parent link might be set.
This kinda relies on waves being launched in order which tends to
be the case on AMD. To avoid the busy-wait loop waiting on stuff
from the same subgroup we do the actual processing in the body of
the loop. This can have performance implications but mostly in the
case we'd otherwise deadlock, so meh.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
First usage of the offset field, Can put more in it in the follow
up.
Reviewed-By: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18799>
This seems like a debug thing, but the blob also seems to use it for
workarounds where an event is required but no actual work needs to be
done. For example CP_REG_WRITE uses it for various workarounds.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023>
Otherwise we use old invalid value.
Relevant CTS tests:
dEQP-VK.pipeline.monolithic.multisample.misc.dynamic_rendering.multi_renderpass.r8g8b8a8_unorm_r16g16b16a16_sfloat_r16g16b16a16_*
Fixes: ed125e6cca
("tu: Initial support for dynamic rendering")
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18999>
we can break on the first NULL resource as frontends always bind
contingous lists of resources without any gaps.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18670>
Dynamic renderpasses need vsc_prim_strm_pitch, vsc_draw_strm_pitch
values, and a correct BO. The easiest way to solve this is to
lazily init VSC when it is needed, and not at every cmdbuf
initialization.
Fixes CTS tests (when running with TU_DEBUG=gmem,forcebin):
dEQP-VK.draw.dynamic_rendering.complete_secondary_cmd_buff.*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18996>
If enabled, use a scoped trace to see where calls happen on frontend vs
where they are pushed down to driver. This is much lighter weight than
printf based tracing, but would still be an extra few instructions even
if perfetto tracing isn't active, so it is not enabled by default.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Use the MESA_TRACE_BEGIN/END() macros which will generate perfetto
traces (if perfetto is enabled) otherwise atrace (if android build), in
either case creating track events which will show up on the frontend
thread in a perfetto trace, giving visibility into where syncs happen.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18927>
Fix#7432: unknown nir_op flrp assertion
This copy-pastes src/gallium/drivers/radeonsi/si_shader_nir.c
The lower_flrp16 value differs given chipset >= NVISA_GV100_CHIPSET.
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19003>
A lot of code zero-initializes pipe_sampler_state, and sets the states
the non-zero fields manually. This means that normalized_coords is the
"default" setting.
However, setting normalized_coords to true isn't allways allowed, and
we'd need to check PIPE_CAP_TEXRECT first. So it's not really the ideal
default here. There's recently been found quite a bit of bugs in this
area, where the state-tracker didn't properly lower texrects.
Let's switch this around to avoid more bugs like this in the future.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18971>
Take the opportunity to prune some ftraces that are not that useful
and fill the buffer pretty fast.
Record time is bumped to 1.2s
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18930>
Instead of relying on a certain BVH layout, this patch traverses the BVH
from the root node which gets rid of any layout requirements.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18967>
When called with FD_BO_PREP_FLUSH as the only op bit set, the intention
is to only sync with the submit-queue.. we shouldn't be calling down to
the kernel (where op==0 gets interpreted as MSM_PREP_READ).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18926>
Fixes:
src/gallium/drivers/r600/sfn/sfn_nir.cpp:832: int r600_shader_from_nir(r600_context*, r600_pipe_shader*, r600_shader_key*): Assertion `shader' failed.
karolherbst said:
> long term r600 should implement PIPE_CAP_SHAREABLE_SHADERS
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18963>
Fixes:
thread '<unnamed>' panicked at 'Context missing features. This should never happen!', ../src/gallium/frontends/rusticl/mesa/pipe/context.rs:44:13
Signed-off-by: Thomas Debesse <dev@illwieckz.net>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18962>
