Commit graph

32650 commits

Author SHA1 Message Date
Tim Rowley
1ebf6fc865 swr/rast: Remove use of C++14 template variable
SWR rasterizer must remain C++11 compliant.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:02:29 -05:00
Tim Rowley
9df5691fff swr/rast: SIMD16 FE remove templated immediates workaround
Fixed properly in gcc-compatible fashion.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:02:23 -05:00
Tim Rowley
404ac6da9e swr/rast: SIMD16 PA - rename Assemble_simd16 to Assemble
For consistency and to support overloading.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:02:17 -05:00
Tim Rowley
6cb20c9f3a swr/rast: FE/Binner - unify SIMD8/16 functions using simdlib types
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:02:12 -05:00
Tim Rowley
6afdc8732c swr/rast: Removed some trailing whitespace caught during review
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:02:06 -05:00
Tim Rowley
4edc5d8305 swr: set caps for VB 4-byte alignment
Needed to compensate for change to fetch jit requiring
alignment.

Fixes regressions in piglit: vertex-buffer-offsets and about
another hundred of the vs-input*byte* tests.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:01:59 -05:00
Tim Rowley
4475583f5e swr/rast: Allow gather of floats from fetch shader with 2-4GB offsets
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-09-06 11:01:39 -05:00
Nicolai Hähnle
45c5c44451 radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bug
When the HS wave is empty, the hardware writes the LS VGPRs starting at
v0 instead of v2. Workaround by shifting them back into place when
necessary. For simplicity, this is always done in the LS prolog.

According to the hardware team, this will be fixed in future chips,
so take that into account already.

Note that this is not a bug fix, as the bug was already worked
around by commit 166823bfd2 ("radeonsi/gfx9: add a temporary workaround
for a tessellation driver bug"). This change merely replaces the
workaround by one that should be better.

v2: add workaround code to shader only when necessary
v3: clarify the prefer_mono comment

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-06 10:02:49 +02:00
Nicolai Hähnle
274f1dace7 amd/common: pass chip_class to ac_dump_reg
Acked-by: Marek Olšák <marek.olsak@amd.com>
2017-09-06 09:59:17 +02:00
Nicolai Hähnle
34124e412f radeonsi/gfx9: always flush DB metadata on framebuffer changes
This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-06 09:57:08 +02:00
Charmaine Lee
c12ef63b69 svga: move index buffer bind flag assertion
The buffer bind flags can be promoted in svga_buffer_handle(), so
move the assertion after it. This has already been done for
vertex buffer in commit 6b4bf7e8be, but it misses the one for
index buffer.

Fixes assertion running WarThunder.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2017-09-05 10:31:18 -06:00
Charmaine Lee
98badd7f6e svga: avoid emitting redundant SetShaderResources and SetVertexBuffers
Minor performance improvement in avoiding binding the same shader resource
or the same vertex buffer for the same slot.

Tested with MTT glretrace.

v2: Per Brian's suggestion, add a helper function to do vertex buffer
    comparision.
v3: Change the helper function to vertex_buffers_equal().

Reviewed-by: Brian Paul <brianp@vmware.com>
2017-09-05 10:31:18 -06:00
Marek Olšák
c3ebac6890 radeonsi/gfx9: implement primitive binning
This increases performance, but it was tuned for Raven, not Vega.
We don't know yet how Vega will perform, hopefully not worse.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-05 12:09:02 +02:00
Marek Olšák
51e10c2770 radeonsi: add more state flags into si_state_dsa
3 flags for primitive binning, 2 flags for out-of-order rasterization
(but that will be done some other time)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-05 12:09:02 +02:00
Marek Olšák
0797eea758 radeonsi/gfx9: don't use BREAK_BATCH and FLUSH_DFSM if DFSM is disabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-05 12:09:02 +02:00
Marek Olšák
fb7ba68f6c radeonsi: eliminate PS color outputs when colormask kills them
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-04 15:10:39 +02:00
Marek Olšák
468c131033 gallium/radeon: sort DBG shader flags according to pipe_shader_type
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-09-04 15:10:39 +02:00
Nicolai Hähnle
50283109aa radeonsi: ensure cache flushes happen before SET_PREDICATION packets
The data is read when the render_cond_atom is emitted, so we must
delay emitting the atom until after the flush.

Fixes: 0fe0320dc0 ("radeonsi: use optimal packet order when doing a pipeline sync")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-04 13:50:57 +02:00
Nicolai Hähnle
097cfe9fde radeonsi: fix ARB_transform_feedback_overflow_query on <= VI
The result written by the shader workaround needs to be written back, or
the CP may read stale data.

Fixes: 78476cfe07 ("radeonsi: enable ARB_transform_feedback_overflow_query")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-04 13:50:54 +02:00
Nicolai Hähnle
55df3d2286 radeonsi: fix compute shader state dumping
Fixes: 420c438589 ("radeonsi: log draw and compute state into log context")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-09-04 13:50:47 +02:00
Nicolai Hähnle
30a2f0dfd4 radeonsi: add an assertion that only two-dimensional constant references are used
v2: remove some redundant checks

Acked-by: Roland Scheidegger <sroland@vmware.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> (v1)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:44:09 +02:00
Nicolai Hähnle
3e4dff4f00 gallium/radeon: always use two-dimensional constant references
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:44:06 +02:00
Nicolai Hähnle
83923a1f17 gallium/tests: always use two-dimensional constant references
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:44:04 +02:00
Nicolai Hähnle
33661190d2 pp: always use two-dimensional constant references
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:44:01 +02:00
Nicolai Hähnle
41fba40776 gallium/hud: always use two-dimensional constant references
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:59 +02:00
Nicolai Hähnle
f143354d06 nine: always generate two-dimensional constant file accesses
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:56 +02:00
Nicolai Hähnle
a852ae3620 tgsi/build: always generate two-dimensional constant file accesses
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:44 +02:00
Nicolai Hähnle
41e342d548 tgsi/ureg: always emit constants (and their decls) as 2D
Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:40 +02:00
Nicolai Hähnle
37dd8e8dee gallium: all drivers should accept two-dimensional constant buffer indexing
Most older drivers seem to just ignore the Dimension setting, so virtually
no changes should be needed.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-09-04 13:43:36 +02:00
Leo Liu
8514c5d078 radeon/uvd: add Define Restart Interval to MJPEG bitstream reconstruction
It adds the capacity to decode MJPEG stream with DRI marker

Signed-off-by: Leo Liu <leo.liu@amd.com>
2017-09-02 21:33:11 -04:00
Leo Liu
3b02a8e9dd radeon/uvd: fix MJPEG quantization table index
Fixes: 130d1f456b ("radeon/uvd: reconstruct MJPEG bitstream")

Signed-off-by: Leo Liu <leo.liu@amd.com>
2017-09-02 21:33:11 -04:00
Rob Clark
dc9e08b0c3 freedreno: skip batch-cache for compute shaders
It is kind of pointless for compute, and avoids issues with apps kicking
off more than 32 compute shaders at once.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-09-02 11:41:20 -04:00
Cherniak, Bruce
43145bbf09 swr: Report format max_samples=1 to maintain support for "fake" msaa.
Accompanying patch "st/mesa: only try to create 1x msaa surfaces for
'fake' msaa" requires driver to report max_samples=1 to enable "fake"
msaa. Previously, 0 and 1 were treated equivalently in st_init_extensions()
and either could enable "fake" msaa.

This patch raises the swr default msaa_max_count from 0 to 1, so that
swr_is_format_supported will report max_samples=1.

Real msaa can still be enabled by exporting SWR_MSAA_MAX_COUNT with a
pow2 value between 2 and 16.

This patch is necessary to prevent an OpenSWR regression resulting from
the st/mesa patch.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102038
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
2017-09-01 11:23:16 -05:00
Samuel Pitoiset
12cbd9a13f radeonsi: move si_vm_fault_occured() to AMD common code
For radv, in order to report VM faults when detected.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-09-01 09:46:32 +02:00
Tobias Klausmann
1c4e6d7ca8 nvc0/ir: propagate immediates to CALL input MOVs
On using builtin functions we have to move the input to registers $0 and $1, if
one of the input value is an immediate, we fail to propagate the immediate:

...
mov u32 $r477 0x00000003 (0)
...
mov u32 $r0 %r473 (0)
mov u32 $r1 $r477 (0)
call abs BUILTIN:0 (0)
mov u32 %r495 $r1 (0)
...

With this patch the immediate is propagated, potentially causing the first MOV
to be superfluous, which we'd remove in that case:

...

mov u32 $r0 %r473 (0)
mov u32 $r1 0x00000003 (0)
call abs BUILTIN:0 (0)
mov u32 %r495 $r1 (0)
...

Shaderdb stats:
total instructions in shared programs : 4893460 -> 4893324 (-0.00%)
total gprs used in shared programs    : 582972 -> 582881 (-0.02%)
total local used in shared programs   : 17960 -> 17960 (0.00%)

                local        gpr       inst      bytes
    helped           0          91         112         112
      hurt           0           0           0           0

v2:
 implement some changes proposed by imirkin, the manual deletion of the dead
 mov is necessary after ea22ac23e0 ("nvc0/ir: unlink values pre- and post-call
 to division function") as the potentially dead mov is unlinked properly,
 causing later passes to not notice the mov op at all and thus not cleaning it
 up. That makes up a big chunk of the regression the above commit caused.
 Keep the deletion of the op where it is, deleting it later unnecessarily blows
 up size of the change.

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-08-31 22:58:06 -04:00
Karol Herbst
b672c3833b nvc0: write 0 to pipeline_statistics.cs_invocations
cs_invocations are currently unsupported, but leaving the field uninitialized
is even worse.

fixes on nvc0:
 * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values
 * KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-08-31 22:57:22 -04:00
Ben Crocker
57c8ead0cd llvmpipe: lp_build_gather_elem_vec BE fix for 3x16 load
Fix loading of a 3x16 vector as a single 48-bit load
on big-endian systems (PPC64, S390).

Roland Scheidegger's commit e827d91756
plus Ray Strode's patch reduce pre-Roland Piglit failures from ~4000 to ~2000.  This patch fixes
three of the four regressions observed by Ray:

- draw-vertices
- draw-vertices-half-float
- draw-vertices-half-float_gles2

One regression remains:
- draw-vertices-2101010

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-09-01 01:20:07 +02:00
Ray Strode
75cb6e3617 gallivm: correct channel shift logic on big endian
lp_build_fetch_rgba_soa fetches a texel from a texture.
Part of that process involves first gathering the element
together from memory into a packed format, and then breaking
out the individual color channels into separate, parallel
arrays.

The code fails to account for endianess when reading the packed
values.

This commit attempts to correct the problem by reversing the order
the packed values are read on big endian systems.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100613
Cc: "17.2" "17.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ray Strode <rstrode@redhat.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-09-01 01:19:13 +02:00
Christian König
214b565bc2 winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2
When the kernel supports it set the local flag and
stop adding those BOs to the BO list.

Can probably be optimized much more.

v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-31 14:55:38 +02:00
Marek Olšák
8b3a257851 radeonsi: set a per-buffer flag that disables inter-process sharing (v4)
For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.

v2: It shouldn't crash anymore, but the kernel will reject the new flag.
v3 (christian): Rename the flag, avoid sending those buffers in the BO list.
v4 (christian): Remove setting the kernel flag for now

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-31 14:55:21 +02:00
Brian Paul
5610911fed svga: include sample count in surface_size() computation
Use MAX2() because sampleCount will be zero for non-MSAA surfaces.
No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-08-30 13:59:14 -06:00
Samuel Pitoiset
0d9117b7bd winsys/amdgpu: add BO to the global list only when RADEON_ALL_BOS is set
Only useful when that debug option is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-30 09:33:59 +02:00
Samuel Pitoiset
59101e771d radeonsi: update dirty_level_mask before dispatching
This fixes a rendering issue with Hitman when bindless textures
are enabled.

Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning from DB to texturing")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-30 09:33:55 +02:00
Brian Paul
88cdf16871 llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSOR
If llvmpipe_set_scissor_states() is never called, we still need to be sure
that derived scissor/clip state is updated.  As of commit 743ad599a9
that function might not be called.

Fixes regressed Piglit gl-1.0-scissor-offscreen -fbo -auto test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101709
Fixes: 743ad599a9 ("st/mesa: don't set 16 scissors and 16 viewports
if they're unused")
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-29 20:49:36 -06:00
Bas Nieuwenhuizen
46dd30d08f ac/debug: Support multiple trace ids for nested IBs.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-08-29 23:05:59 +02:00
Timothy Arceri
0168d1f449 radeonsi: stop leaking nir
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-29 09:46:29 +10:00
Marek Olšák
9c92e82b32 radeonsi: rewrite late alloc VS limit computation
This is still very simple, but it's better than before.

Loosely ported from Vulkan.
2017-08-28 21:45:33 +02:00
Marek Olšák
39205f216e gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmation
Ported from Vulkan.
Not sure what this is good for.. maybe write confirmation from L2 flushes?

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-28 21:45:33 +02:00
Marek Olšák
61187c1689 gallium/u_threaded: rename IGNORE_VALID_RANGE -> NO_INFER_UNSYNCHRONIZED
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-28 21:45:33 +02:00
Marek Olšák
28c4c55810 gallium/u_threaded: disallow discard_range if map_buffer is unsynchronized
The discard range codepath takes precedence, so if we get both
unsynchronized and discard_range, choose unsynchronized.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-28 21:45:32 +02:00