The coefficient register is 16-bit so our builder will make the iter 16-bit too
(maybe not the best design...), force fp32 to match the NIR intrinsic.
Fixes glsl-fs-fragcoord-zw-ortho
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20017>
UBSan complains otherwise:
../src/asahi/compiler/agx_pack.c:701:21: runtime error: left shift of 1 by 31 places cannot be represented in type 'int'
../src/asahi/compiler/agx_pack.c:534:18: runtime error: left shift of 8 by 28 places cannot be represented in type 'int'
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19971>
r5 and r6 are always getting lowered. Will prevent a regression with VBO
lowering on a shader which has stride=0 and hence gets the vertex ID read
optimized out with NIR:
dEQP-GLES2.functional.draw.random.50
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19971>
Flag day change to replace the previous hardcoded background/end-of-tile shaders
and the API-style load/store_output in fragment shaders with the generated
shaders and lowered *_agx intrinsics. This gets us working non-UNORM8 render
targets and working MRT. It's also a step in the direction of working MSAA but
that needs a lot more work, since the multisampling programming model on AGX is
quite different from any of the APIs (including Metal).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
This hw instruction writes out an entire block from the tilebuffer to an
attached render target (PBE descriptor). It is used (only?) in end-of-tile
shaders to implement write out. We need to handle it in the compiler as a
prerequisite to compiling end-of-tile shaders ourselves, instead of hardcoding.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
Mutlisampled texture fetch (txf_ms) is encoded like regular txf. However, we now
need to pack the multisample index in the right place, which we do by extending
our existing NIR texture source lowering pass. 2D MS arrays use a new value of
dim which requires tweaking the encoding slightly. Otherwise, everything is
bog standard.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
This avoids exposing the ISA-internal agx_format to the driver, instead hiding
it behind a real PIPE_FORMAT. This lets us use real pipe formats in formatted
intrinsics in NIR, which is convenient; it will allow us to simplify the
compiler/driver ABI; and it lets us use common format helpers (e.g.
util_format_get_blocksize) for the internal formats in driver lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
With support for MRT in the driver (not included here), passes:
dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.int_highp_fragment
dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.int_highp_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
Otherwise the registers "leak", bloating register pressure by
arbitrarily large amounts. This is easy to handle in DCE by rewriting to
a null destination, though we could use a sideband channel if we didn't
want null destinations in the IR.
glmark2 subset of shader-db is much improved:
total instructions in shared programs: 7324 -> 7313 (-0.15%)
instructions in affected programs: 483 -> 472 (-2.28%)
helped: 5
HURT: 2
total bytes in shared programs: 42788 -> 42722 (-0.15%)
bytes in affected programs: 2808 -> 2742 (-2.35%)
helped: 5
HURT: 2
total halfregs in shared programs: 2421 -> 2058 (-14.99%)
halfregs in affected programs: 1235 -> 872 (-29.39%)
helped: 28
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19590>
Now that everything is in place, we can actually take advantage of
preambles. This wins us a crude form of UBO pushing (accounting for most
of the win here), as well as its intended purpose of optimizing
uniform-on-uniform arithmetic.
shader-db results are excellent. The shader that's regressed for instruction
count is a fragment shader that solely consists of `gl_FragColor = uniform`,
which goes from a vectorized UBO load to four scalar moves. That's more
instructions (and more bytes) but presumably faster, since ALU should be much
cheaper than load/store.
total instructions in shared programs: 6502 -> 5764 (-11.35%)
instructions in affected programs: 5136 -> 4398 (-14.37%)
helped: 60
HURT: 1
helped stats (abs) min: 2.0 max: 47.0 x̄: 12.33 x̃: 8
helped stats (rel) min: 0.84% max: 34.48% x̄: 18.69% x̃: 21.05%
HURT stats (abs) min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33%
95% mean confidence interval for instructions value: -14.69 -9.51
95% mean confidence interval for instructions %-change: -20.49% -15.20%
Instructions are helped.
total bytes in shared programs: 42186 -> 38310 (-9.19%)
bytes in affected programs: 33182 -> 29306 (-11.68%)
helped: 60
HURT: 1
helped stats (abs) min: 10.0 max: 272.0 x̄: 64.83 x̃: 50
helped stats (rel) min: 0.72% max: 30.00% x̄: 15.16% x̃: 16.67%
HURT stats (abs) min: 14.0 max: 14.0 x̄: 14.00 x̃: 14
HURT stats (rel) min: 31.82% max: 31.82% x̄: 31.82% x̃: 31.82%
95% mean confidence interval for bytes value: -77.73 -49.35
95% mean confidence interval for bytes %-change: -16.66% -12.11%
Bytes are helped.
total halfregs in shared programs: 2370 -> 1639 (-30.84%)
halfregs in affected programs: 1804 -> 1073 (-40.52%)
helped: 60
HURT: 0
helped stats (abs) min: 1.0 max: 40.0 x̄: 12.18 x̃: 8
helped stats (rel) min: 3.85% max: 72.73% x̄: 41.37% x̃: 36.17%
95% mean confidence interval for halfregs value: -14.77 -9.60
95% mean confidence interval for halfregs %-change: -46.00% -36.75%
Halfregs are helped.
Total CPU time (seconds): 2.71 -> 2.80 (3.32%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
This pass creates preamble shaders. The heavylifting is done by
nir_opt_preamble. We do need to define the cost model for nir_opt_preamble, set
up 16-bit units for the register file, and scalarize the resulting
load/store_preamble intrinsics.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
This does not seem to be possible architecturally. Exhaustively checked
all bits of the encoding. Avoids regressing
dEQP-GLES3.functional.texture.units.8_units.only_2d.0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
lower_resinfo generates some 64-bit math, so we need to handle it. Even
though we don't have native 64-bit moves, it's convenient to pretend we
do to avoid special cases in the IR. In particular, modelling 64-bit
mov_imm in the IR means our existing small constant propagation code
works, with zero-extension from 8->64.
Fixes dEQP-GLES3.functional.texture.units.2_units.only_2d_array.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
It's useful to be able to copyprop uniform registers into COLLECT. That
requires handling of uniform registers in the parallel copy lowering,
which isn't too hard to add.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
These need to copy values between GPRs and uniform registers. This is pretty
easy in either direction. This implements scalar versions of the intrinsics. A
backend NIR pass will scalarize for us.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
We really need to autogenerate the packing code... It's on the todo
list, currently in discussions on how to best go about this.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
