Commit graph

78782 commits

Author SHA1 Message Date
Tapani Pälli
b91e1e38e8 egl/dri2: set max values for pbuffer width and height
While these max values were previously fixed for pbuffer creation, this
change makes also eglGetConfigAttrib() return correct values.

Fixes following dEQP tests:

   dEQP-EGL.functional.create_surface.pbuffer.rgb888_no_depth_no_stencil
   dEQP-EGL.functional.create_surface.pbuffer.rgb888_depth_stencil
   dEQP-EGL.functional.create_surface.pbuffer.rgba8888_no_depth_no_stencil
   dEQP-EGL.functional.create_surface.pbuffer.rgba8888_depth_stencil

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98326
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
2016-10-25 07:24:11 +03:00
Brian Paul
76c3f1bbbe gallium/stapi: fix comment for st_visual::buffer_mask
Trivial.
2016-10-24 17:22:00 -07:00
Nanley Chery
59385da39d isl/format: Correct ASTC entries of format info table
With the isl_format_supports* helpers, we can now conveniently
report support for this format on Cherry View.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-10-24 15:51:57 -07:00
Kenneth Graunke
41034abfe6 i965: Drop nir_inputs from fs_visitor.
It's unused.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-10-24 14:33:38 -07:00
Kenneth Graunke
59864e8e02 i965: Don't use nir_assign_var_locations for VS/TES/GS outputs.
Fixes spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-dvec3.

v2: Remove nir_outputs field from fs_visitor (caught by Tim and Iago).

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-10-24 14:33:38 -07:00
Kenneth Graunke
27715c73ff i965: Make split_virtual_grfs() call compact_virtual_grfs().
Post-splitting, VGRFs have a maximum size (MAX_VGRF_SIZE).  This is
required by the register allocator, as we have to create classes for
each size of VGRF.

We can (and do) allocate virtual registers larger than MAX_VGRF_SIZE,
but we must ensure that they are splittable.  split_virtual_grfs()
asserts that the post-splitting register size is in range.

Unfortunately, these trip for completely dead registers which are too
large - we only set split points for live registers.  So dead ones are
never split, and if they happened to be too large, they'd trip asserts.

To fix this, call compact_virtual_grfs() to eliminate dead registers
before splitting.

v2: Add a comment written by Iago.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-10-24 14:33:38 -07:00
Kenneth Graunke
3728ee000a i965: Drop unnecessary switch statement in nir_setup_outputs()
TCS and FS are skipped above.  CS has no output variables.
All remaining cases take the same path.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-10-24 14:33:38 -07:00
Brian Paul
88a618ce86 tgsi: trivial build fix for MSVC
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-24 14:16:07 -07:00
Samuel Pitoiset
6dbb8d12a8 nv50/ir: do not perform global membar for shared memory
Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-24 22:51:54 +02:00
Axel Davy
eed605a473 st/nine: Fix locking CubeTexture surfaces.
Only one face of Cubetextures was locked when in DEFAULT Pool.
Fixes:
https://github.com/iXit/Mesa-3D/issues/129

CC: "12.0 13.0" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
fe7bb46134 st/nine: Fix mistake in Volume9 UnlockBox
In the format fallback path,
the height was used instead of the depth.

CC: "12.0 13.0" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
942778099e st/nine: Use align_calloc instead of align_malloc
We are not sure exactly what needs to be 0 initialized,
but we are missing some cases. 0 initialize all our current
aligned allocation.

Fixes Tree of Savior visual issues.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-10-24 21:56:44 +02:00
Axel Davy
54010cf8b6 gallium/util: Add align_calloc
Add implementation for align_calloc,
which is align_malloc + memset.

v2: add if (ptr) before memset.
Fix indentation.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:56:44 +02:00
Axel Davy
25beccb379 st/nine: Fix leak with integer and boolean constants
Leak introduced by:
a83dce0128

The patch also moves the part to
release changed.vs_const_i and changed.vs_const_b
before the if (!cb.buffer_size) check,
to avoid reuploading every draw call if
integer or boolean constants are dirty, but the shaders
use no constants.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
CC: "13.0" <mesa-stable@lists.freedesktop.org>
2016-10-24 21:56:44 +02:00
Marek Olšák
f35b1d156b tgsi/scan: scan texture offset operands
This seems important considering how much we depend on some of the flags.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:38 +02:00
Marek Olšák
a2f98dff14 tgsi/scan: move src operand processing into a separate function
the next commit will need this

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:36 +02:00
Marek Olšák
72267a25db tgsi/scan: get information about shader buffer usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:35 +02:00
Marek Olšák
d89890d000 tgsi/scan: handle indirect image indexing correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:33 +02:00
Marek Olšák
ac37720f51 tgsi/scan: don't treat RESQ etc. as memory instructions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:30 +02:00
Marek Olšák
f095a4eb17 tgsi/scan: get information about indirect 2D file access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:28 +02:00
Marek Olšák
965a5f1810 tgsi/scan: get information about indirect CONST access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-10-24 21:41:26 +02:00
Anuj Phogat
35010718bc i965/gen8: Don't enable alpha test and alpha to coverage if draw bufer zero is integer type
We follow this rule at multiple places in i965 driver. This patch
doesn't fix any testcase.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-24 11:07:39 -07:00
Anuj Phogat
93b84cae54 i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_ps_blend()
No functional changes in this patch.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-24 11:07:39 -07:00
Anuj Phogat
e2dd582de8 i965/gen8: Use DrawBuffer->_IntegerBuffers in gen8_upload_blend_state()
No functional changes in this patch.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-24 11:07:39 -07:00
Samuel Pitoiset
d588e4f192 nv50/ir: display OP_BAR subops in debug mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-24 18:53:45 +02:00
Iago Toral Quiroga
537dce06ec glsl: add matrix layout information to interface block types
So far we have been checking that interface block definitions had matching
matrix layouts by comparing the definitions of their fields, however, this
does not cover the case where the interface blocks are defined with
mismatching matrix layouts but don't define any field with a matrix type.
In this case Mesa will not fail to link because none of the fields will
inherit the mismatching layout qualifier.

This patch fixes the problem in the same way we fixed it for packing layout
information: we add the the layout information to the interface type and then
we check it matches during the uniform block linking process.

v2: Fix unit tests so they pass the new parameter to
    glsl_type::get_interface_instance()

Fixes:
dEQP-GLES31.functional.shaders.linkage.uniform.block.layout_qualifier_mismatch_3

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98245
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
2016-10-24 15:49:53 +02:00
Nicolai Hähnle
3d6b5dee3a st/mesa: cleanup and fix primitive restart for indirect draws
There are three intended functional changes here:

1. OpenGL 4.5 clarifies that primitive restart should only apply with index
   buffers, so make that change explicit in the indirect draw path.

2. Make PrimitiveRestartFixedIndex work with indirect draws.

3. The change where primitive_restart is only set when the restart index can
   actually have an effect (based on the size of indices) is also applied for
   indirect draws.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-24 15:24:23 +02:00
Timothy Arceri
6dbe8a1b9f glsl/mesa: remove unused namespace support from the symbol table
Namespace support seems to have been unused for a very long time.

Previously the hash table entry was never removed and the symbol name
wasn't freed until the symbol table was destroyed.

In theory this could reduced the number of times we need to copy a string
as duplicate names are reused. However in practice there is likely only a
limited number of symbols that are the same and this is likely to cause
other less than optimal behaviour such as the hash_table continuously
growing.

Along with dropping namespace support this change removes entries from
the hash table as they become unused.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2016-10-24 21:40:39 +11:00
Jonathan Gray
907ace5798 mapi: automake: set VISIBILITY_CFLAGS for shared glapi
shared glapi was previously built without setting CFLAGS for
AM_CFLAGS and VISIBILITY_CFLAGS.

This resulted in symbols being exported that shouldn't be.

The x86 and sparc assembly versions of the dispatch table partially
mitigated this by using .hidden.  Otherwise shared_dispatch_stub_*
were being exported.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: "11.2 12.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2016-10-24 11:29:23 +01:00
Emil Velikov
8df581520a anv: automake: cleanup the generated json file during make clean
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-10-24 11:29:12 +01:00
Stencel, Joanna
2e0ab61e29 egl/wayland: add missing destroy_window callback
The original patch by Joanna added the function pointer and callback yet
things got only partially applied - the infra was added, but the
implementation was missing.

Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Fixes: 690ead4a13 ("egl/wayland-egl: Fix for segfault in
dri2_wl_destroy_surface.")
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-10-24 09:50:53 +01:00
Samuel Iglesias Gonsálvez
b50b82b8a5 glsl/es31: precision qualifier doesn't need to match in shader interface block members
It is specific only to GLSL ES 3.1. From the spec, section 4.3.9
"Interface Blocks":

"Matched block names within a shader interface (as defined above) must
 match in terms of having the same number of declarations with the same
 sequence of types and the same sequence of member names, as well as
 having the same qualification as specified in section 9.2 (“Matching
 of Qualifiers“)."

But in GLSL ES 3.0 and 3.2, it is the opposite:

"Matched block names within a shader interface (as defined above) must
 match in terms of having the same number of declarations with the same
 sequence of types, precisions and the same sequence of member names,
 as well as having the matching member-wise layout qualification as
 defined in section 9.2 (“Matching of Qualifiers”)."

Fixes:

dEQP-GLES31.functional.shaders.linkage.uniform.block.differing_precision

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98243
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2016-10-24 07:04:38 +02:00
Samuel Iglesias Gonsálvez
849390a61a glsl: move intrastage_match() after interstage_member_mismatch()
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2016-10-24 07:04:32 +02:00
Dave Airlie
a969548f59 radv: allow cmask transitions without fast clear
This fixes
dEQP-VK.pipeline.multisample.sampled_image*

These all render to multisampled image, and then
sample from it, so we must transition it correctly,
since we have a cmask and fmask this will cause
the correct transition.

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-10-24 11:03:09 +10:00
Ilia Mirkin
7b7eb7170d nv50/ir: it appears that OP_DISCARD can't take a join modifier
nvdisasm does not print a .S even though the bit is set.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-22 12:02:35 -04:00
Ilia Mirkin
adad576bfc nv50/ir: use levelZero for non-frag tex/txp ops
radeonsi also does the same thing. I suspect that this is likely to be a
no-op in reality, but it brings nouveau code closer to what the blob
produces. Plus it makes sense to not try to do auto-derivatives on this.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-22 12:02:35 -04:00
Ilia Mirkin
3fdeb7c983 gallium: add PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
This allows the driver to signal that it can't handle random
interleaving of attributes across buffers. This is required for
ARB_transform_feedback3, and it's initialized to whatever the previous
value of PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME was except for nv50 where
it is disabled. Note that the proprietary drivers never expose
ARB_transform_feedback3 on any GT21x's (where nouveau previously did),
and after some effort I was unable to get it to work.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-22 12:02:35 -04:00
Samuel Pitoiset
6e08f3e96c nvc0/ir: remove outdated comment about SHLADD
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-10-22 14:50:17 +02:00
Eric Anholt
8ff4182876 vc4: Avoid making temporaries for assignments to NIR registers.
Getting stores to NIR regs to not generate new MOVs is tricky, since the
result we're trying to store into the NIR reg may have been from a
conditional update of a temp, or a series of packed writes.  The easiest
solution seems to be to require that nir_store_dest()'s arg comes from an
SSA temp.

This causes us to put in a few more temporary MOVs in the NIR SSA dest
case, but copy propagation successfully cleans those up.

The shader-db change is modest:

total instructions in shared programs: 93774 -> 93598 (-0.19%)
instructions in affected programs:     14760 -> 14584 (-1.19%)
total estimated cycles in shared programs: 212135 -> 211946 (-0.09%)
estimated cycles in affected programs:     27005 -> 26816 (-0.70%)

but I was seeing patterns in some register-allocation failures in DEQP
tests that looked like the extra MOVs would increase maximum register
pressure in loops.  Some debug code indicates that that's not the case,
though I'm still a bit confused by that result.
2016-10-21 14:12:22 -07:00
Eric Anholt
a689b8b9df vc4: Add a comment with discussion of how simulation works. 2016-10-21 14:12:22 -07:00
Eric Anholt
83ffb607b7 vc4: Move simulator winsys mapping and tracking to the simulator.
One tiny hack is left in vc4_bufmgr.c for what kind of mapping we got so
that we can free it.
2016-10-21 14:12:22 -07:00
Eric Anholt
1c38ee380d vc4: Move simulator memory management to a u_mm.h heap.
Now we aren't limited to 256MB total allocated across a driver instance,
just 256MB at one time.  We're still copying in and out, which should get
fixed.
2016-10-21 14:12:22 -07:00
Eric Anholt
9f75522382 vc4: Move simulator globals into a struct.
I would like to put a couple more things in here, so it's time to package
it up.
2016-10-21 14:12:22 -07:00
Eric Anholt
78087676c9 vc4: Restructure the simulator mode.
Rather than having simulator mode changes scattered around vc4_bufmgr.c
and vc4_screen.c, make vc4_bufmgr.c just call a vc4_simulator_ioctl, which
then dispatches to a corresponding implementation.

This will give the simulator support a centralized place to do tricks like
storing most BOs directly in simulator memory rather than copying in and
out.

This leaves special casing of mmaping BOs and execution, because of the
winsys mapping.
2016-10-21 14:12:22 -07:00
Eric Anholt
1d7874fa7b vc4: Fix termination of the initial scan for branch targets.
The loop is scanning until the original max_ip (size of the BO), but we
want to not examine any code after the PROG_END's delay slots.  There was
a block trying to do that, except that we had some early continue
statements if the signal wasn't a PROG_END or a BRANCH.

The failure mode would be that a valid shader is rejected because some
undefined memory after the PROG_END slots is parsed as a branch and the
rest of its setup is illegal.  I haven't seen this in the wild, but
valgrind was complaining and the new userland simulator code started
triggering it.
2016-10-21 14:12:06 -07:00
Jason Ekstrand
7ea4ef8849 anv: Always use the full driver path in the intel_icd.*.json
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-10-21 09:30:23 -07:00
Jason Ekstrand
d96345de98 anv: Suffix the intel_icd file with the host CPU
Vulkan has a multi-arch problem... The idea behind the Vulkan loader is
that you have a little json file on your disk that tells the loader where
to find drivers.  The loader looks for these json files in standard
locations, and then goes and loads the my_driver.so's that they specify.
This allows you as a driver implementer to put their driver wherever on the
disk they want so long as the ICD points in the right place.

For a multi-arch system, however, you may have multiple libvulkan_intel.so
files installed that the loader needs to pick depending on architecture.
Since the ICD file format does not specify any architecture information,
you can't tell the loader where to find the 32-bit version vs. the 64-bit
version.  The way that packagers have been dealing with this is to place
libvulkan_intel.so in the top level lib directory and provide just a name
(and no path) to the loader.  It will then use the regular system search
paths and find the correct driver.  While this solution works fine for
distro-installed Vulkan drivers, it doesn't work so well for user-installed
drivers because they may put it in /opt or $HOME/.local or some other more
exotic location.  In this case, you can't use an ICD json file with just a
library name because it doesn't know where to find it; you also have to add
that to your library lookup path via LD_LIBRARY_PATH or similar.

This patch handles both use-cases by taking advantage of the fact that the
loader dlopen()s each of the drivers and, if one dlopen() calls fails, it
silently continues on to open other drivers.  By suffixing the icd file, we
can provide two different json files: intel_icd.x86_64.json and
intel_icd.i686.json with different paths.  Since dlopen() will only succeed
on the libvulkan_intel.so of the right arch, the loader will happily ignore
the others and load that one.  This allows us to properly handle multi-arch
while still providing a full path so user installs will work fine.

I tested this on my Fedora 25 machine with 32 and 64-bit builds of our
Vulkan driver installed and 32 and 64-bit builds of crucible.  It seems to
work just fine.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-10-21 09:30:20 -07:00
Nicolai Hähnle
17353ef043 radeonsi: fix a regression in si_eliminate_const_output
A constant value of float type is not necessarily a ConstantFP: it could also
be a constant expression that for some reason hasn't been folded.

This fixes a regression in GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2
that was introduced by commit 3ec9975555.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-21 09:59:26 +02:00
Ilia Mirkin
8cf0f05713 nv50,nvc0: don't keep track of whether fb rt0 is integer-only
This reverts commits 1af0641db3 and
a6ad49cbbd.

st/mesa adjusts the rasterizer state for us now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-10-21 02:28:26 -04:00
Francisco Jerez
811eb7f178 Revert "Revert "mapi: export all GLES 3.2 functions in libGLESv2.so""
This reverts commit 85e9bbc14d.  The
previous commit should help with the scons build failure caused by the
original commit.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2016-10-20 15:57:18 -07:00