Commit graph

25650 commits

Author SHA1 Message Date
Marek Olšák
b6d95248f0 radeonsi: move si_shader_binary_upload out of si_shader_binary_read
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
7fa6bb47e3 gallium/radeon: dump LLVM module outside of radeon_llvm_compile
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
fb98acb5a1 gallium/radeon: always add +DumpCode to the LLVM target machine for LLVM <= 3.5
It's the same behavior that we use for later LLVM.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
cd7f252b11 gallium/radeon: r600_can_dump_shader should get TGSI processor type directly
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
fd7000bd78 radeonsi: pass TGSI processor type to si_shader_binary_read for dumping
the parameter will be used later

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
3ce0a2fd7f radeonsi: pass TGSI processor type to si_compile_llvm for dumping
the parameter will be used later

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Marek Olšák
dd79034ca6 radeonsi: rename shader parameter definitions and variables for more clarity
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-03 22:41:16 +01:00
Ilia Mirkin
34217018c4 nvc0/ir: add support for PK2H/UP2H
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-03 16:20:52 -05:00
Ilia Mirkin
e9f43d6333 gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-03 16:20:41 -05:00
Ilia Mirkin
459e4532af tgsi: update PK2H/UP2H channel behavior info
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-03 16:20:27 -05:00
Ilia Mirkin
6eb74b87b8 gallium: document PK2H/UP2H
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-03 16:19:57 -05:00
Rob Clark
3684e899ea freedreno/ir3: use NIR_PASS helper macros
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-03 09:11:27 -05:00
Rob Clark
23bd6affb2 freedreno/ir3: we require block_index metadata
Found during NIR_TEST_CLONE=1 piglit run.  We were using block->index
but forgetting to require it.  Causing things to not work with a cloned
shader which didn't preserve block_index.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-03 09:11:27 -05:00
Rob Clark
74135f804a freedreno/ir3: refactor NIR IR handling
Immediately convert into NIR and do an initial key-agnostic lowering/
optimization pass.  This should let us share most of the per-variant
transformations between each variant, and hopefully minimize the draw-
time variant creation part of the compilation process.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-03 09:11:27 -05:00
Rob Clark
ab4efb19dc freedreno/ir3: drop unnecessary unreachable() case
It will still hit a compile_assert() in emit_tex, which has the
advantage of dumping out the offending shader.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-01-03 09:11:27 -05:00
Samuel Pitoiset
6a49fcfb1f gallium/tests: fix build with clang compiler
Nested functions are supported as an extension in GNU C, but Clang
don't support them.

This fixes compilation errors when (manually) building compute.c,
or by setting --enable-gallium-tests to the configure script.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75165
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-03 12:18:00 +01:00
Samuel Pitoiset
53dddab78c nv50,nvc0: optimize coherent buffer checking at draw time
Instead of iterating over all the buffer resources looking for coherent
buffers, we keep track of a context-wide count. This will save some
iterations (and CPU cycles) in 99.99% case because usually coherent
buffers are not so used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-03 12:17:05 +01:00
Eric Anholt
64253fdb2e vc4: Fix build from upload changes. 2016-01-02 17:33:19 -08:00
Nicolai Hähnle
8f384d07a8 gallium/radeon: send LLVM diagnostics as debug messages
Diagnostics sent during code generation and the every error message reported
by LLVMTargetMachineEmitToMemoryBuffer are disjoint reporting mechanisms. We
take care of both and also send an explicit message indicating failure at the
end, so that log parsers can more easily tell the boundary between shader
compiles.

Removed an fprintf that could never be triggered.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:24 -05:00
Nicolai Hähnle
255ccd1e99 gallium/radeon: pass pipe_debug_callback into radeon_llvm_compile (v2)
This will allow us to send shader debug info via the context's debug callback.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:24 -05:00
Nicolai Hähnle
f8cd11403a radeonsi: send shader info as debug messages in addition to stderr output
The output via stderr is very helpful for ad-hoc debugging tasks, so that remains
unchanged, but having the information available via debug messages as well
will allow the use of parallel shader-db runs.

Shader stats are always provided (if the context is a debug context, that is),
but you still have to enable the appropriate R600_DEBUG flags to get
disassembly (since it is rather spammy and is only generated by LLVM when we
explicitly ask for it).

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:24 -05:00
Nicolai Hähnle
4bb1c8dfec radeonsi: pass pipe_debug_callback down into si_shader_binary_read (v2)
This will allow us to send shader debug info.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:23 -05:00
Nicolai Hähnle
b6847062dd gallium/radeon: implement set_debug_callback
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:23 -05:00
Marek Olšák
ecb2da1559 u_upload_mgr: allow specifying PIPE_USAGE_* for the upload buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:45 +01:00
Marek Olšák
37d0aea772 u_upload_mgr: remove alignment parameter from u_upload_create
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:45 +01:00
Marek Olšák
1bb79c3a7b u_upload_mgr: pass alignment to u_upload_buffer manually
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:44 +01:00
Marek Olšák
e0f932846c u_upload_mgr: pass alignment to u_upload_data manually
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:44 +01:00
Marek Olšák
020009f7cc u_upload_mgr: pass alignment to u_upload_alloc manually
The fixed alignment of u_upload_mgr will go away.
This is the first step.

The motivation is that one u_upload_mgr can have multiple users,
each allocating from the same buffer, but requiring a different alignment.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:44 +01:00
Marek Olšák
ffc4716e97 u_upload_mgr: rework the application of alignment
The function only aligned the size, but not the offset.
The offset was aligned only when the previous suballocation was aligned.
That yielded the correct offset alignment if the alignment was constant
for all suballocations.

Instead, directly align the offset, but allow an unaligned size.
There is no change in behavior, because the alignment is constant
at the moment.

This a prerequisite for allowing a variable alignment for suballocations.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:44 +01:00
Ilia Mirkin
c1d14c6817 nv50,nvc0: make sure there's pushbuf space and that we ref the bo early
First off, we can't flush in the middle of a command. Secondly
requesting the extra push space might cause a flush to happen. If that
flush happens, we'd have to do the PUSH_REFN again. So instead do
PUSH_REFN after the push space request. This helps avoid rare crashes
with supertuxkart in libdrm due to assertion failures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2016-01-01 19:52:41 -05:00
Kenneth Graunke
65d3f85eb3 nvc0: Set winding order regardless of domain.
Quads need to respect winding order, too - not just triangles.

Fixes rendering in GFXBench 4.0's tessellation benchmark.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-30 16:04:12 -08:00
Ilia Mirkin
517a93b346 nvc0: add ARB_shader_draw_parameters support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-30 16:55:57 -05:00
Ilia Mirkin
daaf0bdf46 gallium: add a drawid to pipe_draw_info
This will allow the state tracker to inform the driver where in a
broken-up multidraw we currently are. This can then be passed into the
vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-12-30 16:55:56 -05:00
Ilia Mirkin
87b4e4e29f gallium: add PIPE_CAP_DRAW_PARAMETERS
This allows the state tracker to know that the various draw parameters
are available in vertex shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-12-30 16:55:56 -05:00
Ilia Mirkin
bb52ea45cc gallium: add baseinstance/drawid semantics
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-12-30 16:55:56 -05:00
Ilia Mirkin
d50e6128b8 nv50/ir: attempt to do more constant folding on mad -> add conversion
The add might actually have a 0 as an argument, which would convert it
into a mov. Make sure to detect that. Also avoid the hack of putting the
immediate directly into the instruction, instead use a mov to put it
into place and let the later LoadPropagation pass place it if possible.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-30 12:29:07 -05:00
Jason Ekstrand
0119773ffc nir/builder: Add an init function that creates a simple shader for you
A hugely common case when using nir_builder is to have a shader with a
single function called main.  This adds a helper that gives you just that.
This commit also makes us use it in the NIR control-flow unit tests as well
as tgsi_to_nir and prog_to_nir.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-29 13:44:05 -08:00
Ilia Mirkin
724134f683 nv50/ir: float(s32 & 0xff) = float(u8), not s8
Make sure to make conversion unsigned when we're ANDing the high bits
away. Fixes corruption in dolphin.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-29 15:08:20 -05:00
Nicolai Hähnle
7b8db37abb radeonsi: add RADEON_REPLACE_SHADERS debug option
This option allows replacing a single shader by a pre-compiled ELF object
as generated by LLVM's llc, for example. This can be useful for debugging a
deterministically occuring error in shaders (and has in fact helped find
the causes of https://bugs.freedesktop.org/show_bug.cgi?id=93264).

v2: drop the debug flag, use DEBUG_GET_ONCE_OPTION instead

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-29 09:07:04 -05:00
Nicolai Hähnle
7d1fc2cf51 radeonsi: count compilations in si_compile_llvm
This changes the count slightly (because of si_generate_gs_copy_shader), but
this is only relevant for the driver-specific num-compilations query. It sets
the stage for the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-29 09:07:01 -05:00
Nicolai Hähnle
4711170239 gallium/util: add DEBUG_GET_ONCE_OPTION
This is analogous to the alreading existing macros for BOOL, NUM, and FLAGS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-29 09:06:57 -05:00
Grazvydas Ignotas
da0e216e06 r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as
size, which prevents the hardware from fetching the correct values.
Fix it by combining shift and align so that the value is always
rounded up.

Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-12-29 09:05:55 -05:00
Jason Ekstrand
237f2f2d8b nir: Get rid of function overloads
When Connor originally drafted NIR, he copied the same function+overload
system that GLSL IR had with a few names changed.  However, this
double-indirection is not really needed and has only served to confuse
people.  Instead, let's just have functions which may not have unique names
and may or may not have an implementation.  If someone wants to do overload
resolving, they can hav a hash table based function+overload system in the
overload resolving pass.  There's no good reason to keep it in core NIR.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

ir3 bits are

Reviewed-by: Rob Clark <robclark@gmail.com>
2015-12-28 09:59:53 -08:00
Ilia Mirkin
109c348284 nvc0: don't forget to reset VTX_TMP bufctx slot after blit completion
Also release the scratch allocation if any.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-27 21:33:36 -05:00
Ilia Mirkin
28e07fdd4a nv50,nvc0: add a note when converting vertex elements using CPU
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-12-27 19:49:44 -05:00
Connor Abbott
41c7912d04 gallium/auxiliary: don't build NIR sources with MSVC2008 flags
NIR has never been built with MSVC2008, so we shouldn't add
MSVC2008_COMPAT_CFLAGS to anything that uses it. This allows us to get
rid of the pragma in tgsi_to_nir.c.

Build tested with freedreno.

v2: Use MSVC2013_COMPAT_CLFAGS instead.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
2015-12-23 20:46:48 -05:00
Rob Clark
843cec6d3a freedreno/ir3: spelling..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-12-23 00:28:24 -05:00
Kenneth Graunke
7d539080c1 nir: Add a writemask to store intrinsics.
Tessellation control shaders need to be careful when writing outputs.
Because multiple threads can concurrently write the same output
variables, we need to only write the exact components we were told.

Traditionally, for sub-vector writes, we've read the whole vector,
updated the temporary, and written the whole vector back.  This breaks
down with concurrent access.

This patch prepares the way for a solution by adding a writemask field
to store_var intrinsics, as well as the other store intrinsics.  It then
updates all produces to emit a writemask of "all channels enabled".  It
updates nir_lower_io to copy the writemask to output store intrinsics.

Finally, it updates nir_lower_vars_to_ssa to handle partial writemasks
by doing a read-modify-write cycle (which is safe, because local
variables are specific to a single thread).

This should have no functional change, since no one actually emits
partial writemasks yet.

v2: Make nir_validate momentarily assert that writemasks cover the
    complete value - we shouldn't have partial writemasks yet
    (requested by Jason Ekstrand).

v3: Fix accidental SSBO change that arose from merge conflicts.

v4: Don't try to handle writemasks in ir3_compiler_nir - my code
    for indirects was likely wrong, and TTN doesn't generate partial
    writemasks today anyway.  Change them to asserts as requested by
    Rob Clark.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3]
2015-12-22 15:57:59 -08:00
Ben Skeggs
a8c4747602 nouveau: enable use of new kernel interfaces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-22 13:24:17 +10:00
Ben Skeggs
5b614b141a nvc0: remove use of deprecated sw class identifier
Also emits a method to properly bind the class to a subchannel, which
was missing previously.  The kernel currently doesn't care, but this
will break if it ever decides to (ie. to support multiple sw classes).

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2015-12-22 13:24:13 +10:00