This is already done for a6xx. For everyone else move it out of the
common code path and into fd_layout_resource_for_handle().
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
Explicitly layout the resource in all cases, rather than depending on
the partial/incomplete layout that is done in fd_resource_from_handle()
(which will be going away).
Now that we are not YOLOing the layout, it turns up some questionable
assumptions in piglit. Just mark those xfails for now.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
And rename it to layout_resource_for_handle. The handle contains
additional information such as the pitch/offset for the imported
buffer.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
Export the existing helper, and call it from the legacy backends which
are not using fdl.
This moves all the layout initialization to the backends (and eventually
to fdl for the backends using that).
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
Pass the layout type to setup_slices, renamed to layout_resource, to
move some of the partial layout initialization to the gen specific
backend.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
We already use fdl_layout_buffer() when the resource is allocated. But
it was missed to convert fd_resource_resize(). Convert it so there is
no path into ->setup_slices() with something that is a buffer.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
fdl6_layout() (and to a lesser degree) fdl5_layout() is growing an
unwieldly argument list, and it isn't obvious at first glance what
fdl_layout fields should be initialized before calling it. So split
out a fdl_image_params struct to clean this up.
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36075>
Previously, we would only offset register ids for LValues that are
directly used in a merge/split instruction, but this is incorrect.
We instead need to apply the offset to all LValues that compMask
has been propagated to. By calcuating this from compMask instead
of figuring it out a second time, we fix that issue and also manage
to simplify the code a bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
This code previously stored two rather different masks in compMask:
1. from merge/splits (calculated in makeCompound), and
2. in the join root for whatever register was assigned
Since we were already calculating the second type as intfMask where it
is used in checkInterference(), change that function to unconditionally
use intfMask and only use compMask for the first type.
This is functionally equavalent and keeps the types of masks separate.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24541>
It's non-trivial to drop the private binding or transfer ownership to
the bound memory. So we track the image in the device memory for
dedicated allocation so that wsi image alias can find the original wsi
image from the wsi memory.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36095>
Lowering IO to temps leads to problems with RA with piglit
spec@glsl-1.50@execution@geometry@max-input-component
Not doing so results in an assertion failure with piglit
spec@glsl-1.50@execution@geometry@dynamic_input_array_index
because not all indirect IO access is lowered. Using
nir_lower_indirect_derefs works around this limitations.
v2: Fix formatting (Patrick Lerda)
Fixes: 1186c73c6 (r600: implement gs indirect load_per_vertex_input)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36051>
I've overlooked that unconditionallowering of indirect VS
inputs had been dropped. Since VS inputs are stored in
consecutive registers one can implement the indirect access
without additional lowering, it just needs a proper declararion
of the registers forming the array.
v2: - Fix formatting (Patrick Lerda)
- Use allocator for std::map to avvoid menory leak
(Patrick Lerda)
Fixes: a43bfffe1e
r600: Correct nir_indirect_supported_mask
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36051>
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
This commit proposes an optimized version using Arm A32 NEON
intrinsics.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
Payload size retrieval can greatly benefit from using SIMD to sum up
the 16 6-bit packed sizes. This commit proposes an optimized version
using Arm A64 NEON intrinsics. This was measured on a Rock 5B to be ~2
times faster than the original.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
The AFBC-P payload layout is currently retrieved in 2 steps starting
with the payload sizes retrieval using a CS job on the GPU followed by
a CPU pass to set the payload offsets. This commit proposes to do both
steps on the CPU at once using a new utility function
pan_afbc_payload_layout_packed().
A new utility function pan_afbc_payload_uncompressed_size() is added
to help retrieve the uncompressed size from a pipe_format and
modifier. Both the CPU and GPU versions use it now.
A new AFBC-P driconf option "pan_afbcp_gpu_payload_sizes" is added to
fallback to the original payload sizes retrieval on the GPU.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
Add an AFBC header block structure pan_afbc_headerblock to improve
readability when accessing header blocks. get_superblock_size(), which
will be used for AFBC packing in the next commits, has been moved to
pan_afbc.h and renamed to pan_afbc_payload_size() so that it can be
tested. Other utility functions pan_afbc_header_subblock_size() and
pan_afbc_header_subblock_uncompressed_size() hasve been added to help
retrieve the compressed or uncompressed size of a subblock from a
header. This commit also fixes a few issues like arch handling.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
Print the AFBC-P state of a resource along its asynchronous packing
process when PAN_MESA_DEBUG=forcepack. There's no need to prevent
tiling in that case now that packing maintains the tiling state.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
Pack AFBC resources asynchronously in order to prevent stalls at
texture upload waiting for 1) the AFBC staging blit (sparse encoding)
to complete and 2) the AFBC payload sizes retrieval.
After a texture upload, an AFBC resource is now progressively packed
at each read access once consecutively accessed a certain number of
times without a write access. This allows to prevent most stalls by
making AFBC packing a progressive async background process.
A useful side effect is that consecutive glTexSubImage*() calls on the
same texture (for texture atlases for instance) don't uselessly
respawn packing.
A new AFBC-P driconf option "pan_afbcp_reads_threshold" is added to
tweak the consecutive reads threshold.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
It isn't used outside of pan_resource.c.
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35001>
