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radeonsi: rename sctx->has_graphics to sctx->is_gfx_queue

Browse source 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
This commit is contained in:
Yogesh Mohan Marimuthu 2025-07-02 12:13:41 +05:30 • committed by Marge Bot
parent 761496b49e
commit b55ee5f335
16 changed files with 43 additions and 43 deletions
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2
src/gallium/drivers/radeonsi/si_barrier.c
View file

@ -40,7 +40,7 @@ static unsigned get_reduced_barrier_flags(struct si_context *ctx)
if (!flags)
return 0;
if (!ctx->has_graphics) {
if (!ctx->is_gfx_queue) {
/* Only process compute flags. */
flags &= SI_BARRIER_INV_ICACHE | SI_BARRIER_INV_SMEM | SI_BARRIER_INV_VMEM |
SI_BARRIER_INV_L2 | SI_BARRIER_WB_L2 | SI_BARRIER_INV_L2_METADATA |

4
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -1426,7 +1426,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
* If blitter is running, we can't decompress DCC either because it
* will cause a blitter recursion.
*/
if (!tex->surface.meta_offset || !sctx->has_graphics || sctx->blitter_running)
if (!tex->surface.meta_offset || !sctx->is_gfx_queue || sctx->blitter_running)
return;
si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level, 0,
@ -1437,7 +1437,7 @@ void si_init_blit_functions(struct si_context *sctx)
{
sctx->b.resource_copy_region = si_resource_copy_region;
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
sctx->b.blit = si_blit;
sctx->b.flush_resource = si_flush_resource;
sctx->b.generate_mipmap = si_generate_mipmap;

4
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -1274,7 +1274,7 @@ static bool si_try_normal_clear(struct si_context *sctx, struct pipe_surface *ds
dst->last_layer == util_max_layer(dst->texture, dst->level) &&
/* pipe->clear honors render_condition, so only use it if it's unset or if it's set and enabled. */
(!sctx->render_cond || render_condition_enabled) &&
sctx->has_graphics) {
sctx->is_gfx_queue) {
struct pipe_context *ctx = &sctx->b;
struct pipe_framebuffer_state saved_fb = {}, fb = {};
@ -1446,7 +1446,7 @@ void si_init_clear_functions(struct si_context *sctx)
sctx->b.clear_render_target = si_clear_render_target;
sctx->b.clear_texture = u_default_clear_texture;
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
if (sctx->gfx_level >= GFX12)
sctx->b.clear = gfx12_clear;
else

12
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -696,7 +696,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
/* Set PING_PONG_EN for every other dispatch.
* Only allowed on a gfx queue, and PARTIAL_TG_EN and USE_THREAD_DIMENSIONS must be 0.
*/
if (sctx->has_graphics && !partial_block_en &&
if (sctx->is_gfx_queue && !partial_block_en &&
!sctx->cs_shader_state.program->sel.info.uses_atomic_ordered_add) {
dispatch_initiator |= S_00B800_PING_PONG_EN(sctx->compute_ping_pong_launch);
sctx->compute_ping_pong_launch ^= 1;
@ -745,7 +745,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
* - COMPUTE_START_X/Y are in units of 2D subgrids, not workgroups
* (program COMPUTE_START_X to start_x >> log_x, COMPUTE_START_Y to start_y >> log_y).
*/
if (sctx->has_graphics && !partial_block_en &&
if (sctx->is_gfx_queue && !partial_block_en &&
(info->indirect || info->grid[1] >= 4) && MIN2(info->block[0], info->block[1]) >= 4 &&
si_get_2d_interleave_size(info, &log_x, &log_y)) {
dispatch_interleave = S_00B8BC_INTERLEAVE_1D(1) || /* 1D is disabled */
@ -754,7 +754,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
dispatch_initiator |= S_00B800_INTERLEAVE_2D_EN(1);
}
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
radeon_opt_set_sh_reg_idx(R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE,
SI_TRACKED_COMPUTE_DISPATCH_INTERLEAVE, 2, dispatch_interleave);
} else {
@ -886,7 +886,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
si_check_dirty_buffers_textures(sctx);
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
if (sctx->num_draw_calls_sh_coherent.with_cb != sctx->num_draw_calls ||
sctx->num_draw_calls_sh_coherent.with_db != sctx->num_draw_calls) {
bool sync_cb = sctx->force_shader_coherency.with_cb ||
@ -941,7 +941,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
si_compute_resources_add_all_to_bo_list(sctx);
/* Skipping setting redundant registers on compute queues breaks compute. */
if (!sctx->has_graphics) {
if (!sctx->is_gfx_queue) {
BITSET_CLEAR_RANGE(sctx->tracked_regs.reg_saved_mask,
SI_FIRST_TRACKED_OTHER_REG, SI_NUM_ALL_TRACKED_REGS - 1);
}
@ -976,7 +976,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
/* Registers that are not read from memory should be set before this: */
si_emit_barrier_direct(sctx);
if (sctx->has_graphics && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
if (sctx->is_gfx_queue && si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
sctx->atoms.s.render_cond.emit(sctx, -1);
si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
}

6
src/gallium/drivers/radeonsi/si_compute_blit.c
View file

@ -756,7 +756,7 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
.use_aco = sctx->screen->use_aco,
.no_fmask = sctx->screen->debug_flags & DBG(NO_FMASK),
/* Compute queues can't fail because there is no alternative. */
.fail_if_slow = sctx->has_graphics && fail_if_slow,
.fail_if_slow = sctx->is_gfx_queue && fail_if_slow,
};
struct ac_cs_blit_description blit = {
@ -782,7 +782,7 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
.box = info->src.box,
.format = info->src.format,
},
.is_gfx_queue = sctx->has_graphics,
.is_gfx_queue = sctx->is_gfx_queue,
/* if (src_access || dst_access), one of the images is block-compressed, which can't fall
* back to a pixel shader on radeonsi */
.dst_has_dcc = vi_dcc_enabled(sdst, info->dst.level) && !src_access && !dst_access,
@ -800,7 +800,7 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info,
return true;
/* This is needed for compute queues if DCC stores are unsupported. */
if (sctx->gfx_level < GFX10 && !sctx->has_graphics && vi_dcc_enabled(sdst, info->dst.level))
if (sctx->gfx_level < GFX10 && !sctx->is_gfx_queue && vi_dcc_enabled(sdst, info->dst.level))
si_texture_disable_dcc(sctx, sdst);
/* Shader images. */

4
src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
View file

@ -11,7 +11,7 @@
bool si_init_cp_reg_shadowing(struct si_context *sctx)
{
if (sctx->has_graphics &&
if (sctx->is_gfx_queue &&
sctx->screen->info.has_kernelq_reg_shadowing) {
if (sctx->screen->info.has_fw_based_shadowing) {
sctx->shadowing.registers =
@ -51,7 +51,7 @@ bool si_init_cp_reg_shadowing(struct si_context *sctx)
if (!si_init_gfx_preamble_state(sctx))
return false;
if (sctx->has_graphics && sctx->screen->info.has_kernelq_reg_shadowing) {
if (sctx->is_gfx_queue && sctx->screen->info.has_kernelq_reg_shadowing) {
/* We need to clear the shadowed reg buffer. */
si_cp_dma_clear_buffer(sctx, &sctx->gfx_cs, &sctx->shadowing.registers->b.b,
0, sctx->shadowing.registers->bo_size, 0);

6
src/gallium/drivers/radeonsi/si_cp_utils.c
View file

@ -26,7 +26,7 @@ static bool is_ts_event(unsigned event_type)
void si_cp_release_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
unsigned event_type, unsigned gcr_cntl)
{
assert(sctx->gfx_level >= GFX11 && sctx->has_graphics);
assert(sctx->gfx_level >= GFX11 && sctx->is_gfx_queue);
bool ts = is_ts_event(event_type);
/* Extract GCR_CNTL fields because the encoding is different in RELEASE_MEM. */
assert(G_586_GLI_INV(gcr_cntl) == 0);
@ -94,7 +94,7 @@ void si_cp_acquire_mem_pws(struct si_context *sctx, struct radeon_cmdbuf *cs,
unsigned event_type, unsigned stage_sel, unsigned gcr_cntl,
unsigned distance, unsigned sqtt_flush_flags)
{
assert(sctx->gfx_level >= GFX11 && sctx->has_graphics);
assert(sctx->gfx_level >= GFX11 && sctx->is_gfx_queue);
bool ts = is_ts_event(event_type);
bool cs_done = event_type == V_028A90_CS_DONE;
bool ps = event_type == V_028A90_PS_DONE;
@ -157,7 +157,7 @@ void si_cp_acquire_mem(struct si_context *sctx, struct radeon_cmdbuf *cs, unsign
radeon_emit(gcr_cntl); /* GCR_CNTL */
radeon_end();
} else {
bool compute_ib = !sctx->has_graphics;
bool compute_ib = !sctx->is_gfx_queue;
/* This seems problematic with GFX7 (see #4764) */
if (sctx->gfx_level != GFX7)

2
src/gallium/drivers/radeonsi/si_debug.c
View file

@ -23,7 +23,7 @@ DEBUG_GET_ONCE_OPTION(replace_shaders, "RADEON_REPLACE_SHADERS", NULL)
static enum amd_ip_type si_get_context_ip_type(struct si_context *sctx)
{
return sctx->has_graphics ? AMD_IP_GFX : AMD_IP_COMPUTE;
return sctx->is_gfx_queue ? AMD_IP_GFX : AMD_IP_COMPUTE;
}
/**

4
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -2853,7 +2853,7 @@ static void si_emit_gfx_resources_add_all_to_bo_list(struct si_context *sctx, un
void si_init_all_descriptors(struct si_context *sctx)
{
int i;
unsigned first_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
unsigned first_shader = sctx->is_gfx_queue ? 0 : PIPE_SHADER_COMPUTE;
unsigned hs_sgpr0, gs_sgpr0;
if (sctx->gfx_level >= GFX12) {
@ -2949,7 +2949,7 @@ void si_init_all_descriptors(struct si_context *sctx)
sctx->b.delete_image_handle = si_delete_image_handle;
sctx->b.make_image_handle_resident = si_make_image_handle_resident;
if (!sctx->has_graphics)
if (!sctx->is_gfx_queue)
return;
sctx->b.set_polygon_stipple = si_set_polygon_stipple;

2
src/gallium/drivers/radeonsi/si_fence.c
View file

@ -54,7 +54,7 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne
EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) |
event_flags;
unsigned sel = EOP_DST_SEL(dst_sel) | EOP_INT_SEL(int_sel) | EOP_DATA_SEL(data_sel);
bool compute_ib = !ctx->has_graphics;
bool compute_ib = !ctx->is_gfx_queue;
radeon_begin(cs);

4
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -132,7 +132,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
ctx->gfx_flush_in_progress = true;
if (ctx->has_graphics) {
if (ctx->is_gfx_queue) {
if (!list_is_empty(&ctx->active_queries))
si_suspend_queries(ctx);
@ -534,7 +534,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs)
radeon_end();
}
if (!ctx->has_graphics) {
if (!ctx->is_gfx_queue) {
ctx->initial_gfx_cs_size = ctx->gfx_cs.current.cdw;
return;
}

10
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -202,7 +202,7 @@ static void si_destroy_context(struct pipe_context *context)
util_framebuffer_init(context, NULL, sctx->framebuffer.fb_cbufs, &sctx->framebuffer.fb_zsbuf);
si_release_all_descriptors(sctx);
if (sctx->gfx_level >= GFX10 && sctx->has_graphics)
if (sctx->gfx_level >= GFX10 && sctx->is_gfx_queue)
si_gfx11_destroy_query(sctx);
if (sctx->sqtt) {
@ -514,7 +514,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
return NULL;
}
sctx->has_graphics = sscreen->info.gfx_level == GFX6 ||
sctx->is_gfx_queue = sscreen->info.gfx_level == GFX6 ||
/* Compute queues hang on Raven and derivatives, see:
* https://gitlab.freedesktop.org/mesa/mesa/-/issues/12310 */
((sscreen->info.family == CHIP_RAVEN ||
@ -558,7 +558,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
goto fail;
}
if (!ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? AMD_IP_GFX : AMD_IP_COMPUTE,
if (!ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->is_gfx_queue ? AMD_IP_GFX : AMD_IP_COMPUTE,
(void *)si_flush_gfx_cs, sctx)) {
mesa_loge("can't create gfx_cs");
sctx->gfx_cs.priv = NULL;
@ -659,7 +659,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
si_init_context_texture_functions(sctx);
/* Initialize graphics-only context functions. */
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
if (sctx->gfx_level >= GFX10)
si_gfx11_init_query(sctx);
si_init_msaa_functions(sctx);
@ -751,7 +751,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
}
sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
unsigned start_shader = sctx->is_gfx_queue ? 0 : PIPE_SHADER_COMPUTE;
for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
sctx->b.set_constant_buffer(&sctx->b, shader, i, false, &sctx->null_const_buf);

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1000,7 +1000,7 @@ struct si_context {
bool blitter_running:1;
bool suppress_update_ps_colorbuf0_slot:1;
bool is_noop:1;
bool has_graphics:1;
bool is_gfx_queue:1;
bool gfx_flush_in_progress : 1;
bool gfx_last_ib_is_busy : 1;
bool compute_is_busy : 1;

2
src/gallium/drivers/radeonsi/si_query.c
View file

@ -1958,7 +1958,7 @@ void si_init_query_functions(struct si_context *sctx)
sctx->b.get_query_result = si_get_query_result;
sctx->b.get_query_result_resource = si_get_query_result_resource;
if (sctx->has_graphics) {
if (sctx->is_gfx_queue) {
sctx->atoms.s.render_cond.emit = si_emit_query_predication;
sctx->b.render_condition = si_render_condition;
}

20
src/gallium/drivers/radeonsi/si_state.c
View file

@ -5013,13 +5013,13 @@ static bool gfx6_init_gfx_preamble_state(struct si_context *sctx)
bool has_clear_state = sscreen->info.has_clear_state;
/* We need more space because the preamble is large. */
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->is_gfx_queue);
if (!pm4) {
mesa_loge("failed to allocate memory for cs_preamble_state");
return false;
}
if (sctx->has_graphics && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
@ -5037,7 +5037,7 @@ static bool gfx6_init_gfx_preamble_state(struct si_context *sctx)
si_init_compute_preamble_state(sctx, pm4);
if (!sctx->has_graphics)
if (!sctx->is_gfx_queue)
goto done;
/* Graphics registers. */
@ -5099,13 +5099,13 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx)
struct si_screen *sscreen = sctx->screen;
/* We need more space because the preamble is large. */
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->is_gfx_queue);
if (!pm4) {
mesa_loge("failed to allocate memory for cs_preamble_state");
return false;
}
if (sctx->has_graphics && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
@ -5123,7 +5123,7 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx)
si_init_compute_preamble_state(sctx, pm4);
if (!sctx->has_graphics)
if (!sctx->is_gfx_queue)
goto done;
/* Graphics registers. */
@ -5171,26 +5171,26 @@ static bool gfx12_init_gfx_preamble_state(struct si_context *sctx)
{
struct si_screen *sscreen = sctx->screen;
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 300, sctx->has_graphics);
struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 300, sctx->is_gfx_queue);
if (!pm4) {
mesa_loge("failed to allocate memory for cs_preamble_state");
return false;
}
if (sctx->has_graphics && !sctx->shadowing.registers) {
if (sctx->is_gfx_queue && !sctx->shadowing.registers) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
}
if (sctx->has_graphics && sscreen->dpbb_allowed) {
if (sctx->is_gfx_queue && sscreen->dpbb_allowed) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
}
si_init_compute_preamble_state(sctx, pm4);
if (!sctx->has_graphics)
if (!sctx->is_gfx_queue)
goto done;
/* Graphics registers. */

2
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -488,7 +488,7 @@ bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex)
{
struct si_screen *sscreen = sctx->screen;
if (!sctx->has_graphics)
if (!sctx->is_gfx_queue)
return si_texture_discard_dcc(sscreen, tex);
if (!si_can_disable_dcc(tex))