FDO_HTTP_CACHE_URI is not defined, but LAVA_HTTP_CACHE_URI is and is the
right URL for this.
This job is currently disabled, but fix it in preparation for when
someone eventually brings it back.
Note that this line also has another bug that will be addressed by the
next commit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36955>
Without this, I get failures in the following CTS test:
dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
Fixes: 05006c21dd ("panvk/utrace: Alloc utrace copy buf from userspace heap")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36980>
There is a FW issue when using constrained intra prediction with rate
control enabled, causing unexpected quality degradation.
Disable it until FW fix is available.
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36837>
RADV_DYNAMIC_RASTERIZATION_SAMPLES triggers the following states:
- FS (not needed when FS is NULL)
- MSAA (already triggered)
- BINNING (use radv_get_ps_iter_samples() on GFX9)
- OCCLUSION_QUERY (doesn't use the PS)
- DB_SHADER_CONTROL (already triggered)
- RAST_SAMPLES (use radv_get_ps_iter_samples())
- NGGC (doesn't use the PS)
So this can be simplified to BINNING (gfx9) | RAST_SAMPLES.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36912>
This reduces the number of states that are re-emitted but the logic
is mostly duplicated because sample shading can be set from the
fragment shader or the graphics pipeline. Could be refactored
eventually.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36912>
This is already handled slightly above in the same function. Also
state->dirty isn't for RADV_DYNAMIC_xxx and there is no corresponding
RADV_CMD_DIRTY_xxx either.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36912>
Right now, we store the last VkDeviceMemory object bound to an image in
panvk_image::mem, but this doesn't work for disjoint images where the mem
object can differ on each plane.
Move panvk_image::mem to panvk_image_plane::mem and prefix the offset
field with mem_, so it's clear the offset refers to the mem object.
Note this should only fix host copy on disjoint images, since the GPU
address was already properly set at bind time.
Fixes: 1cd61ee948 ("panvk: implement VK_EXT_host_image_copy for linear color images")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36926>
Commit c11f47481a ("panvk: stop CPU mapping all index buffers on JM")
stopped mapping the buffer objects on v9-, but it forgot to remove
panvk_buffer::host_ptr and panvk_cmd_graphics_state::host_addr.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36934>
Images aren't always coherent with L2 and AMD generations have
different rules, see radv_image_is_l2_coherent() for the full picture.
This fixes a rendering issue on GFX9 because depth/stencil images
aren't coherent, but this also affects color images.
This also fixes a cache coherency issue with an ongoing extension.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12274
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36815>
Based on the previous commit, we can also remove the dynamic allocation
for command memory from the submit path and use the new pool instead.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36609>
utrace requires some memory to allocate buffers for timestamps and
indirect data each submit. It is expensive to allocate it from the
kernel each time. Instead, allocate a big bo upfront and hand it out
in small pieces later using util_vma_heap.
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36609>
This should fix a deadlock I saw on
dEQP-EGL.functional.sharing.gles2.multithread.random.programs.link.7 on
radeonsi, where we were waiting on an invalid fence[1] value. This was
probably because between when we started setting up the fences for
u_queue_finish and when we waited on those fences, a second thread was
created.
Closes: #13738
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36919>
We pass the tests for exchange, load, and store on R32_SFLOAT, including
shared memory (which the proprietary driver does not advertise). The blob
does not support add operations either.
Passes:
dEQP-VK.glsl.atomic_operations.exchange_float*
dEQP-VK.image.atomic_operations.exchange*r32f*
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36907>
In some situations the implementation of `BITSET_EXTRACT` would read
beyond the size of the bitset due to an unconditional + 1 in the address
calculation.
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Fixes: 0cc9443e9b ("util: Add BITSET_EXTRACT")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34605>
f2f640f35 introduces base variants, so we get 2 NIR shaders:
glsl-to-nir -> base_serialized_nir
-> serialized_nir
Then, depending on who is using the shader the right one would be picked:
* draw uses base_serialized_nir
* hw driver uses serialized_nir
ef0c9231a7 made sure that base wasn't used when the shader is loaded from
the cache because it's missing, so in this case, glsl-to-nir does:
glsl-to-nir -> from-cache -> serialized_nir
The problem is that if draw tries to use this shader it may fail, for
the same reason as the referenced commits were introduced: draw may not
be compatible with some NIR passes used by the driver.
To fix this we need to serialize both NIR shaders, and pick the right
one depending on the user.
Fixes: ef0c9231a7 ("mesa/st: don't use serialized_nir for cached shaders")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36411>
Multiple contexts can use those causing deadlocks if e.g. fence_get_fd
gets called before fence_server_signal on another thread on the same
pipe_fence_handle.
Cc: mesa-stable
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36819>
GPFIFO class changed a bit with the years and some
things doesn't parse well on those traces so let's allow to decode with
Ampere A GPFIFO if we are decoding Ampere or later.
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36093>
Disk cache is disabled on Android because by default it is
managed by EGL_ANDROID_blob_cache layer. However there are cases
or custom Android builds where disk cache is needed, then it can be
explicitly enabled via `mesa.shader.cache.disable=false` property
and cache path must be set via `mesa.shader.cache.dir`.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36821>
