fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 02:28:10 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: add a new dirty bit for the VGT prim state

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36912>
This commit is contained in:
Samuel Pitoiset 2025-08-21 18:29:09 +02:00 • committed by Marge Bot
parent 4096009ea1
commit 12f8508363
2 changed files with 12 additions and 9 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3401,7 +3401,7 @@ radv_emit_depth_bias_state(struct radv_cmd_buffer *cmd_buffer)
}
static void
radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
radv_emit_vgt_prim_state(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -3425,6 +3425,8 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
radeon_end();
radv_emit_vgt_gs_out(cmd_buffer, vgt_gs_out_prim_type);
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VGT_PRIM_STATE;
}
static bool
@ -5393,13 +5395,6 @@ lookup_ps_epilog(struct radv_cmd_buffer *cmd_buffer)
static void
radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const uint64_t states)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
if ((states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) ||
(pdev->info.gfx_level >= GFX12 && states & RADV_DYNAMIC_PATCH_CONTROL_POINTS))
radv_emit_primitive_topology(cmd_buffer);
/* RADV_DYNAMIC_ATTACHMENT_FEEDBACK_LOOP_ENABLE is handled by radv_emit_db_shader_control. */
cmd_buffer->state.dirty_dynamic &= ~states;
@ -11482,6 +11477,10 @@ radv_validate_dynamic_states(struct radv_cmd_buffer *cmd_buffer, uint64_t dynami
if (dynamic_states & RADV_DYNAMIC_TESS_DOMAIN_ORIGIN)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE;
if ((dynamic_states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) ||
(pdev->info.gfx_level >= GFX12 && dynamic_states & RADV_DYNAMIC_PATCH_CONTROL_POINTS))
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VGT_PRIM_STATE;
}
static void
@ -11589,6 +11588,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_SCISSOR_STATE)
radv_emit_scissor_state(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VGT_PRIM_STATE)
radv_emit_vgt_prim_state(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PATCH_CONTROL_POINTS_STATE)
radv_emit_patch_control_points_state(cmd_buffer);

3
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -117,7 +117,8 @@ enum radv_cmd_dirty_bits {
RADV_CMD_DIRTY_SCISSOR_STATE = 1ull << 31,
RADV_CMD_DIRTY_TESS_DOMAIN_ORIGIN_STATE = 1ull << 32,
RADV_CMD_DIRTY_PATCH_CONTROL_POINTS_STATE = 1ull << 33,
RADV_CMD_DIRTY_ALL = (1ull << 34) - 1,
RADV_CMD_DIRTY_VGT_PRIM_STATE = 1ull << 34,
RADV_CMD_DIRTY_ALL = (1ull << 35) - 1,
RADV_CMD_DIRTY_SHADER_QUERY = RADV_CMD_DIRTY_NGG_STATE | RADV_CMD_DIRTY_TASK_STATE,
};