Commit graph

25886 commits

Author SHA1 Message Date
Ilia Mirkin
b4688c4615 nvc0: double per-shader stage driver constants area
We need to store a lot more info now with per-buffer address/size.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-29 21:06:06 -05:00
Ilia Mirkin
ae725d5746 trace: add support for set_shader_buffers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add arg_begin/arg_end around buffer array
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-01-29 21:05:47 -05:00
Ilia Mirkin
6fb8fac853 st/mesa: add shader buffer barrier bit
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-29 21:05:47 -05:00
Ilia Mirkin
2ccc42fd2c tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsics
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
v1 -> v2: add defines for the various bits
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-01-29 21:04:36 -05:00
Michel Dänzer
30fcf241e1 winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*
In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created
in VRAM if they get evicted to GTT. In general there's no need to
restrict any of the flags to any particular domains.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-01-29 16:06:06 +09:00
Michel Dänzer
62f837e2ea winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESS
Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to tiled BOs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862

(This change shouldn't be backported to stable branches, because
released versions of xf86-video-amdgpu unnecessarily try to map the
front buffer)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-01-29 16:06:06 +09:00
Karol Herbst
29d09f8747 nv50/ir: optimize mad/fma with third argument 0 to mul
Very modest effect, but it's clearly the right thing to do.

total instructions in shared programs : 6131491 -> 6131398 (-0.00%)
total gprs used in shared programs    : 910157 -> 910131 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst      bytes
    helped           0          55          85          85
      hurt           0          26          20          20

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-28 15:59:41 -05:00
Karol Herbst
3aa681449e nv50/ir: run DCE backwards
Reduces calls up to 50%

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-28 15:34:29 -05:00
Karol Herbst
978ae28ca2 nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))
Following shader-db results on GK110:

total instructions in shared programs : 6141510 -> 6131491 (-0.16%)
total gprs used in shared programs    : 910187 -> 910157 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

                local        gpr       inst      bytes
    helped           0          18         821         821
      hurt           0           0           0           0

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-28 15:34:22 -05:00
Axel Davy
dda7a84986 radeonsi: Add option for SI scheduler
Add a debug option to select the LLVM SI Machine Scheduler.
R600_DEBUG=sisched

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-28 17:22:44 +01:00
Eric Anholt
3fba517bdd vc4: Throttle outstanding rendering after submission.
Just make sure that after we've submitted, we get to at least 5
(global) submits ago before we go on to do more.  Prevents up to
seconds of lag with window movement in X with xcompmgr -c.  There may
be useful tuning to do in the future, but for now this gets us
usability.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2016-01-27 20:05:37 -08:00
Eric Anholt
2a449ce7c9 vc4: Don't record the seqno of a failed job submit.
On an error return, the returned seqno will probably be unset, so we'd
lose track of what we've submitted so far for waiting on in the
future.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2016-01-27 20:05:37 -08:00
Karol Herbst
19ae5de981 nv50/ir: fix memory corruption when spilling and redoing RA
When RA fails, and we spill, we have to clean everything up before doing
RA again. We were forgetting to reset the hi/lo linked lists - at
least the hi list is guaranteed to still have pointers to now-deleted
RIG nodes.

Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2016-01-26 17:55:06 -05:00
Jan Vesely
efc4142acd r600,compute: Plug few memory leaks
v2: drop inline keyword
    drop radeon_llvm_dispose_kernel_module wrapper

v3: move definitions to .c file
    use in radeonsi

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 19:04:38 +01:00
Jan Vesely
e1dcd333e4 r600: Typos and whitespace fixes
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-26 19:01:22 +01:00
Marek Olšák
2924ca131f radeonsi: fix clover crash
caused by ce1e7784d0

Trivial.
2016-01-26 18:53:41 +01:00
Marek Olšák
af57507e4f radeonsi: fix shader precompilation for shader-db
The addition of spi_shader_col_format killed all color outputs
in precompiled shaders.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)

v2: also set the alpha func (trivial)
2016-01-26 18:49:50 +01:00
Emil Velikov
eb63640c1d glsl: move to compiler/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-26 16:08:33 +00:00
Emil Velikov
a39a8fbbaa nir: move to compiler/
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-26 16:08:30 +00:00
Emil Velikov
1a882fd2ee nir: move shader_enums.[ch] to compiler
This way one can reuse it in glsl, nir or other infrastructure without
pulling nir as dependency.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-01-26 16:08:20 +00:00
Nicolai Hähnle
41875ac4ed gallium/ddebug: add 'verbose' option
This currently just writes out the name of dump files, which can be useful
to easily correlate those files with other log outputs (driver debug output,
apitrace calls, etc.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 09:58:55 -05:00
Nicolai Hähnle
f4c8fa4e49 gallium/ddebug: make 'noflush' also affect 'always' mode
This changes the default behavior of 'always' mode to be consistent with
hang detection mode.

I have used this to more easily compare dumped command streams using diff.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 09:58:49 -05:00
Nicolai Hähnle
8894b5f008 radeonsi: use llvm.amdgcn.s.barrier instead of llvm.AMDGPU.barrier.local
The new name for the intrinsic was introduced in LLVM r258558.

v2: use ternary operator instead of preprocessor

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-26 09:57:06 -05:00
Nicolai Hähnle
1067e6eb55 radeonsi: add DCC buffer for sampler views on new CS
This fixes a VM fault and possible lockup in high memory pressure situations.

Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-25 10:16:12 -05:00
Nicolai Hähnle
0bacbf5b7e radeonsi: emit rw_buffers for tes_shader only if tes_shader present
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:08 -05:00
Nicolai Hähnle
2385b253c6 radeonsi: do not set the shader->key for gs copy shaders
The key for a geometry shader would be interpreted as the key for a vertex
shader further down the line, which really doesn't make sense.

This does not affect the contents of shader->key because geometry shaders
don't have any key entries anyway.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:05 -05:00
Nicolai Hähnle
46c0ba60c6 radeonsi: si_llvm_emit_vs_epilogue is never used with gs copy shaders
Hence remove the misleading branch on is_gs_copy_shader.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:02 -05:00
Nicolai Hähnle
c55b9499d5 radeonsi: move is_gs_copy_shader to si_shader_context
It is only used during shader creation now, so no need to keep it around
afterwards.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:16:00 -05:00
Nicolai Hähnle
a7754ffd31 radeonsi: replace use of is_gs_copy_shader in si_shader_vs
We now have an explicit parameter that contains the same information, and
this will allow us to get rid of is_gs_copy_shader in the si_shader struct.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:55 -05:00
Nicolai Hähnle
004fcd4230 radeonsi: ensure that VGT_GS_MODE is sent when necessary
Specifically, when the API switches from using a GS to not using a GS and then
back to using the same GS again, we do not have to re-send all the GS state,
but we do have to send VGT_GS_MODE. So make VGT_GS_MODE consistently be a part
of the VS state.

This fixes a rendering bug in Dolphin, but surely other applications are
affected as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93648
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:31 -05:00
Nicolai Hähnle
9f89bd69df radeonsi: extract the VGT_GS_MODE calculation into its own function
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-25 10:15:08 -05:00
Samuel Pitoiset
429371f22a trace: fix a segfault when tracing indirect draw calls
Like other resources, the indirect draw buffer must be unwrapped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-01-24 19:53:53 +01:00
Marek Olšák
e707b9d8ba winsys/amdgpu: optionally use buffer lists with all allocated buffers
Set RADEON_ALL_BOS=1 to use it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-23 17:01:54 +01:00
Rob Herring
7ee8954753 virgl: enable building on Android
This is just a copy-n-paste and rename of vc4 Android makefiles.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-01-23 12:35:29 +10:00
Marek Olšák
cd9c07e7cd radeonsi: add ETC1 support for Stoney
It's a subset of ETC2. Tested.

For more information, see page 42 and onward:
http://www.graphicshardware.org/previous/www_2007/presentations/strom-etc2-gh07.pdf

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
b3bac55621 radeonsi: change LLVM intrinsics for BREV, CLAMP, EX2
Requested by Matt Arsenault.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
ce1e7784d0 radeonsi: add max waves / SIMD to shader stats (v2)
v2: account for LDS usage in PS
    the limit is per SIMD, not per CU

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
5944f3d2fc radeonsi: enable late VS allocation (v3)
v2: take the number of CUs into account
v3: change in LS allocation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Marek Olšák
97648229e4 radeonsi: allow using all CUs for tessellation and on-chip GS (v2)
v2: After more discussion with hw teams, the kernel already contains the
    optimal settings allowing us to use all CUs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 22:05:42 +01:00
Nicolai Hähnle
d76bd85c35 Revert "radeonsi: fix discard-only fragment shaders (v2)"
This reverts commit 843855bbf0.

It became redundant due to Marek's earlier pushed 8667a1ae which achieves
the same thing.
2016-01-22 12:40:26 -05:00
Nicolai Hähnle
843855bbf0 radeonsi: fix discard-only fragment shaders (v2)
When a fragment shader is used that has no outputs but does conditional
discard (KILL_IF), all fragments are killed without this patch.

By comparing various register settings, my conclusion is that the exec mask
is either not properly forwarded to the DB by NULL exports or ends up being
unused, at least when there is _only_ a NULL export (the ISA documentation
claims that NULL exports can be used to override a previously exported exec
mask).

Of the various approaches I have tried to work around the problem, this one
seems to be the least invasive one.

v2: take discard by alpha test into account as well

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93761
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-22 11:59:50 -05:00
Marek Olšák
a9d5842ec0 radeonsi: add ETC2 support for Stoney
Tested and working.
2016-01-22 15:36:14 +01:00
Marek Olšák
6f428328d3 radeonsi: implement SAMPLEPOS system value without a constant buffer load
We always get per-sample input position.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
2b66bc87d4 winsys/amdgpu: compute num_good_compute_units correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
0d8e4f958f gallium/radeon: rename max_compute_units -> num_good_compute_units
radeon sets this correctly, but not amdgpu

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
99dfeb01bd radeonsi: disable SPI color outputs the shader doesn't write
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
f6360de8c0 radeonsi: use all SPI color formats
because not using SPI_SHADER_32_ABGR doubles fill rate.

We should also get optimal performance if alpha isn't needed or blending
isn't enabled.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
933e3c4145 radeonsi: use 32_AR for alpha-to-coverage without a color buffer
This avoids the fp16 packing instructions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
f1f0158837 radeonsi: add shader conversion code for all SPI color formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
Marek Olšák
e28b8530b9 radeonsi: set CB_SHADER_MASK according to SPI color formats
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00