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Author SHA1 Message Date
Corbin Simpson
c4fa0e4caa r300g: Remove faulty assert. 2009-11-07 13:07:52 -08:00
Corbin Simpson
b7322fd874 Merge branch 'r300g-vbo' 
This is an experimental HW TCL fastpath for r300g. It should run alright.

Thanks to osiris for making this possible.
 2009-11-07 12:03:04 -08:00
Corbin Simpson
0fe5f0c09a r300g: Be more verbose in what's killing us WRT vert formats. 2009-11-07 11:55:29 -08:00
Corbin Simpson
cd5b2a93d5 r300g: Comments. 2009-11-07 11:55:29 -08:00
Corbin Simpson
ef513776b5 r300g: Don't assert on oversized VBOs, just return FALSE. 2009-11-07 11:55:25 -08:00
Corbin Simpson
746c01b3b2 r300g: Moar vbo cleanup. 2009-11-07 11:53:14 -08:00
Corbin Simpson
b6c3954138 r300g: s/false/FALSE/ 
Also s/true/TRUE/
 2009-11-07 11:53:14 -08:00
Corbin Simpson
7da3cc4241 r300g: Clean up indexbuf render, switch to RELOC macro. 2009-11-07 11:53:14 -08:00
Corbin Simpson
7518d9b1b7 r300g: Clean up r300_setup_vertex_buffers. 2009-11-07 11:53:14 -08:00
Corbin Simpson
96b729f926 r300g: Don't pass hw_prim around in the context. 
And some other fixes.
 2009-11-07 11:53:14 -08:00
Corbin Simpson
24c6fdbd32 r300g: Use common state funcs for translating vert formats. 2009-11-07 11:53:14 -08:00
Maciej Cencora
1ef0341ea7 r300g: don't hang GPU on misbehaving apps 2009-11-07 11:53:13 -08:00
Maciej Cencora
3445f47697 r300g: VBOs WIP 2009-11-07 11:53:13 -08:00
Maciej Cencora
d8592d1724 r300g: add missing flush 2009-11-07 11:53:13 -08:00
Maciej Cencora
c7dfffc5d5 r300g: enable CS dumping 2009-11-07 11:53:13 -08:00
Maciej Cencora
6acb26eadf r300g: move vborender context function to seperate file 
r300g: Un-migrate r300_draw_render.

It'll make maintaining the SW TCL path easier.
 2009-11-07 11:53:06 -08:00
Jakob Bornecrantz
57d77c6a44 i915g: Fix comment in is buffer referenced 2009-11-07 19:31:18 +00:00
brian
18768393d1 mesa: move code after decl 
Fixes bug 24967.
 2009-11-07 08:18:07 -07:00
Christoph Bumiller
44cb5b5c66 nv50: enable all 32 threads of a warp 
This should be the default setting.
See also 7d967b9b7c.
 2009-11-07 10:48:36 +01:00
Eric Anholt
8baee3d25b i965: Use Compr4 instruction compression mode on G4X and newer. 
No statistically significant performance difference at n=3 with either
openarena or my GL demo, but cutting program size seems like a good
thing to be doing for the hypothetical app that has a working set near
icache size.
 2009-11-06 21:24:22 -08:00
Eric Anholt
ec66644ed0 i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c 2009-11-06 21:08:55 -08:00
Eric Anholt
cfa927766a i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c 
This should fix issues with antialiased lines in GLSL.
 2009-11-06 21:08:55 -08:00
Eric Anholt
2b58c31257 i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c 
The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's
had been improved, and pixel_w should no longer stomp on a neighbor to dst.
 2009-11-06 21:08:55 -08:00
Eric Anholt
1e5400c575 i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. 2009-11-06 21:08:54 -08:00
Eric Anholt
7059aa0eff i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. 2009-11-06 21:08:54 -08:00
Eric Anholt
726ad15606 i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c 2009-11-06 21:08:54 -08:00
Eric Anholt
bad5b120be i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c 2009-11-06 21:08:54 -08:00
Eric Anholt
06c1bc8a22 i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. 2009-11-06 21:08:54 -08:00
Eric Anholt
90629704ef i965: Use a normal alu1 emit for OPCODE_TRUNC. 2009-11-06 21:08:54 -08:00
Eric Anholt
71af508072 i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c 
This drops support for get_src_reg_imm in these, but the prospect of getting
brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
 2009-11-06 21:08:54 -08:00
Eric Anholt
0f34cdf621 i965: Collect GLSL src/dst regs up in generic code. 
This matches brw_wm_emit.c, which we'll be using shortly.  There's a
possible penalty here in that we'll allocate registers for unused channels,
since we aren't doing ref tracking like brw_wm_pass*.c does.  However, my
measurements on GM965 don't show any for either OA or UT2004 with the GLSL
path forced.
 2009-11-06 21:08:54 -08:00
Zack Rusin
e521bf7706 st/xorg: implement batching for the composite op 
something is broken so disabled for now
 2009-11-06 22:08:21 -05:00
Zack Rusin
4322346f3f st/xorg: batch solid fill requests 
instead of lots of very small transfers, one larger is a lot better
for performance
 2009-11-06 22:08:21 -05:00
Zack Rusin
e1730632aa st/xorg: start accumulating vertices in a common buffer 2009-11-06 22:08:21 -05:00
Zack Rusin
3f7df23ff5 st/xorg: use quads instead of triangle fans 
easier to split, accumulate and batch those
 2009-11-06 22:08:21 -05:00
Zack Rusin
6c44d399bd st/xorg: make the buffer size global 2009-11-06 22:08:21 -05:00
Ian Romanick
26d2ce0a09 GLX: Change GLX client vendor string to "Mesa Project and SGI" 
This change allows a certain closed-source browser plug-in to work
with open-source drivers.
 2009-11-06 14:52:49 -08:00
Eric Anholt
6b0bcfafab mesa: Reduce the source channels considered in optimization passes. 
Depending on the writemask or the opcode, we can often trim the source
channels considered used for dead code elimination.  This saves actual
instructions on 965 in the non-GLSL path for glean glsl1, and cleans up
the writemasks of programs even further.
 2009-11-06 14:27:35 -08:00
Eric Anholt
f3cacfe216 mesa: Fix remove_instructions to successfully remove when removeFlags[0]. 
This fixes the dead code elimination to work on the particular code
mentioned in the previous commit.
 2009-11-06 13:16:49 -08:00
Eric Anholt
e4e312d493 mesa: Add an optimization path to remove use of pointless MOVs. 
GLSL code such as:
	vec4 result = {0, 1, 0, 0};
	gl_FragColor = result;

emits code like:
  0: MOV TEMP[0], CONST[0];
  1: MOV OUTPUT[1], TEMP[0];

and this replaces it with:
  0: MOV TEMP[0], CONST[0];
  1: MOV OUTPUT[1], CONST[0];

Even when the dead code eliminator fails to clean up a now-useless MOV
instruction (since it doesn't do live/dead ranges), this should at reduce
dependencies.
 2009-11-06 13:16:49 -08:00
Eric Anholt
ee0a9e6e10 mesa: Fix up the remove_dead_code pass to operate on a channel basis. 
This cleans up a bunch of instructions in GLSL programs to have limited
writemasks, which would translate to wins in shaders that hit the i965
brw_wm_glsl.c path by depending less on in-driver optimizations.  It will
also help hit other optimization passes I'm looking at.
 2009-11-06 13:16:49 -08:00
Brian Paul
3105f3aa88 intel: better front color buffer test in intelClear() 2009-11-06 13:52:48 -07:00
Eric Anholt
8395da2e8a i965: Always pass the size argument to brw_cache_data. 
This keeps the individual state files from having to export their
structures for brw_state_cache initialization.
 2009-11-06 11:37:32 -08:00
Eric Anholt
1166294d1d intel: Finish removing the fallback code for bug #16697. 
I fixed it properly as of 7216679c19.
 2009-11-06 11:37:32 -08:00
Eric Anholt
75bdbdd90b intel: Don't validate in a texture image used as a render target. 
Otherwise, we could lose track of rendering to that image, which could
easily happen during mipmap generation.
 2009-11-06 11:37:32 -08:00
Eric Anholt
6b68482e68 mesa: Attempt to pair up Driver.RenderTexture and FinishRenderTexture() 
This is probably not 100% complete (bind vs unbind may still not pair up
exactly), but it should help out drivers which are relying on
FinishRenderTexture to be called when we're done rendering to a particular
texture level, not just when we're done rendering to the object at all.
This is the case for the one consumer of FinishRenderTexture() so far: the
gallium state tracker.  Noticed when trying to make use of FRT() in the intel
driver.
 2009-11-06 11:37:32 -08:00
Eric Anholt
8df81bca17 intel: Clean up some extra struct indirection in finalize. 2009-11-06 11:37:32 -08:00
Eric Anholt
ee7dfbbd6c intel: Use _mesa_get_current_tex_object() to clean up TFP path. 2009-11-06 11:37:31 -08:00
Eric Anholt
8f30ceaaef intel: Remove duplicated arguments from intel_miptree_match_image(). 2009-11-06 11:37:31 -08:00
Eric Anholt
2bc8bcdcd3 i965: Remove an XXX comment for testing some code that seems to work. 2009-11-06 11:37:31 -08:00