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Author SHA1 Message Date
Simon Perretta
b111b8a844 pvr, pco: implement prerequisites for sampleRateShading 
- Implement load_interpolated_input and friends.
- Optimize load_barycentric_* cases that can be simplified.
- Initial support for non-standard sample locations.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37540>
 2025-09-27 23:45:54 +01:00
Simon Perretta
83aecc8f3f mesa/st, nir: commonize unlower_io_to_vars pass 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37540>
 2025-09-27 23:45:54 +01:00
Aleksi Sapon
8949473023 nir: Fix nir.h MSVC compilation for C++ source files 
This kind of C initializer is not accepted by MSVC in C++ mode.

Fixed: 75292ae7 ("nir: Fix gnu-empty-initializer warning ")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37604>
 2025-09-26 18:25:22 +00:00
Georg Lehmann
46a4569c22 nir/opt_undef: prefer 0 over NaN for pack_half_2x16_rtz_split
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Using NaN doesn't usually allow any extra optimizations, and 0 is an inline
constant on AMD hw where this opcode is used with undef for fragment shader
exports.

Foz-DB GFX1201:
Totals from 889 (1.11% of 80287) affected shaders:
Instrs: 1676365 -> 1676348 (-0.00%)
CodeSize: 8827040 -> 8821760 (-0.06%)
Latency: 13346728 -> 13346699 (-0.00%)
InvThroughput: 1799283 -> 1799262 (-0.00%)
Copies: 108125 -> 108102 (-0.02%)
VALU: 974875 -> 974852 (-0.00%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37552>
 2025-09-26 15:11:26 +00:00
Aleksi Sapon
75292ae7e4 nir: Fix gnu-empty-initializer warning
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This also causes a build error on older MSVC.

Fixes: 75381670 ("nir,rusticl: NIR_PASS/nir_pass! validation fixes and improvements")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37569>
 2025-09-25 18:14:22 +00:00
Daniel Schürmann
e1a692f74b nir/opt_offsets: allow for unsigned wraps when folding load/store_shared2_amd offsets 
Totals from 131 (0.16% of 79839) affected shaders: (Navi48)

Instrs: 217026 -> 216541 (-0.22%); split: -0.24%, +0.01%
CodeSize: 1150136 -> 1146772 (-0.29%); split: -0.31%, +0.02%
Latency: 4225732 -> 4225549 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 840231 -> 839823 (-0.05%); split: -0.05%, +0.00%
VClause: 3815 -> 3816 (+0.03%)
Copies: 15414 -> 15358 (-0.36%); split: -0.38%, +0.02%
PreSGPRs: 6322 -> 6323 (+0.02%)
PreVGPRs: 6064 -> 6062 (-0.03%)
VALU: 117317 -> 116873 (-0.38%); split: -0.40%, +0.02%
SALU: 25384 -> 25331 (-0.21%); split: -0.22%, +0.02%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
 2025-09-24 14:28:24 +00:00
Rhys Perry
7538167096 nir: add NIR_DEBUG=progress_validation 
Fails if a shader was changed but the pass didn't report progress.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:28 +00:00
Rhys Perry
706ba80057 nir: fix NIR_DEBUG=extended_validation 
This broke after divergence became metadata because the divergence
analysis pass does not support all instructions.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:28 +00:00
Rhys Perry
026e2527bf nir/opt_if: rewrite progress reporting and metadata invalidation 
This would unconditionally invalid all metadata except
nir_metadata_control_flow and then invalidate that if opt_if_safe_cf_list
and opt_if_regs_cf_list made no progress.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Rhys Perry
da23b17c8b nir/opt_if: fix progress reporting with multiple function impls 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Rhys Perry
12ee2b0fd4 nir: fix progress reporting in nir_io_add_const_offset_to_base 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Pierre-Eric Pelloux-Prayer
81f3a5a035 nir/opcodes: remove invalid comment
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"\b" is interpreted by python which results in an invalid char being
written to the C file.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37331>
 2025-09-23 09:09:55 +02:00
Pierre-Eric Pelloux-Prayer
cc4b50b023 nir/opcodes: use u_overflow to fix incorrect checks 
Operands of an addition will be promoted to int making the a+b<a
kind of checks ineffective.

Use u_overflow.h helpers to perform the check correctly.
The commit would be simpler if it used __typeof__ like so:

   util_add_check_overflow(__typeof__(src0), src0, src1)

But typeof only became a standard in C23 so this commit instead extends
nir_opcodes a bit to allow opcodes that need the dest_type to get it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37331>
 2025-09-23 09:09:55 +02:00
Simon Perretta
7b7fb811ab pvr, pco: switch to clc load/store sr and idfwdf shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:05 +01:00
Simon Perretta
c2127bf4f7 pvr, pco: switch to usc generated clear attachment shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Simon Perretta
6dd0a5ee2d pvr, pco: switch to clc query shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Simon Perretta
3fd3d7ee69 pvr, pco: switch to clc vertex passthrough shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:04 +01:00
Simon Perretta
96e4026273 nir: print loop unroll info if present 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37439>
 2025-09-22 14:52:03 +01:00
Timothy Arceri
870ce22754 nir: fix uniform cloning helper again
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UBOs in different stages can have the same instance name for
different UBOs so here we make sure to also check that types match
before deciding we have a match.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13254
Fixes: b47b8d16d9 ("nir: expose reusable linking helpers for cloning uniform loads")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37428>
 2025-09-18 22:28:54 +00:00
Alyssa Rosenzweig
c0c70cb392 nir/lower_flatshade: clean up 
while in the area.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37448>
 2025-09-18 13:37:03 +00:00
Mary Guillemard
d9b11cd7a2 nir/print: Fix load_converted_output_pan and load_readonly_output_pan 
We were not printing IO infos properly for those intrinsics.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37452>
 2025-09-18 10:41:50 +00:00
Gert Wollny
3b3c3ccf56 nir+r600: add option to avoid contracting fabs into ffma
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On r600 ternary operations can't use the fabs source modifier, so
converting "fadd(fabs(fmul(a, b), c)" to  "ffma(fabs(a), fabs(b), c)"
adds one more instruction in the backend, hence avoid this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37440>
 2025-09-17 21:03:58 +00:00
Christian Gmeiner
a7d2570296 nir/opt_algebraic: optimize f2i32(fround_even(x)) to f2i32_rtne(x) 
Add late optimization to fuse f2i32 and fround_even operations into a
single f2i32_rtne instruction when the intermediate fround_even result
is only used once. This eliminates redundant rounding since f2i32_rtne
performs round-to-nearest-even conversion directly.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37426>
 2025-09-17 20:31:59 +00:00
Karmjit Mahil
9c6183604f nir, ir3: Add lower_fmulz_with_abs_min backend option 
This commits adds the `lower_fmulz_with_abs_min` which lowers
`fmulz` -> `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`
`ffmaz` -> `min(abs(a), abs(b)) == 0.0 ? c : ffma(a, b, c)

This is useful for ISAs which have `abs` for free on `min` such as
ir3.

Adreno A750 Benchmark of 10 runs of 5 DX9 single frame trimmed
captures looped 2048 times using u_trace measuring
`start_render_pass` to `end_render_pass` results:

sysmem:
-1.91156%, -2.21791%, -2.02533%, -2.21666%, -2.33272%,
-2.67349%, -1.75278%, -2.05923%, -2.26892%, -2.10506%
Avg:  ~ -2.16%
ST.S: ~  0.25%

gmem:
-3.61496%, -3.66682%, -3.80901%, -3.51198%, -3.72950%,
-3.71413%, -3.64467%, -3.67092%, -3.90640%, -3.83888%
Avg:  ~ -3.71%
ST.S: ~  0.12%

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Karmjit Mahil
8d19ffef0a nir: Add more matches for fmulz 
In some cases after other passes, `(a == 0.0 ? 0 : b)` can be
turned into `(a != 0.0 ? b : 0)`, so let's match those cases too.

Also matching `min(abs(a), abs(b)) == 0.0 ? 0.0 : a * b`.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31479>
 2025-09-17 15:02:50 +00:00
Rhys Perry
810d4ff299 nir/lower_atomics: set ACCESS_COHERENT 
The lack of ACCESS_COHERENT was probably fine, the worst it would do would
add a pointless iteration after loading an out-of-date value.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Rhys Perry
e819160705 nir/lower_atomics_to_ssbo: set ACCESS_COHERENT for loads 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37417>
 2025-09-17 11:29:21 +00:00
Ella Stanforth
753af683b5 pco: Switch to common alpha_to_coverage intrinsic 
Signed-off-by: Ella Stanforth <ella@igalia.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:43 +00:00
Ella Stanforth
5ab606ccda nir: assert when we do not have a sample count when not using intrinsic 
Signed-off-by: Ella Stanforth <ella@igalia.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:42 +00:00
Simon Perretta
6edb72d28b pco: replace {un,}packing alu ops with intrinsics 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:19 +00:00
Simon Perretta
8104ef4e01 pco: support 1010102 snorm, [us]scaled formats 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:19 +00:00
Simon Perretta
c3325b22d8 pco: image atomics support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
672541d036 nir, asahi: commonize interleave_agx 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
a67120cda3 pvr, pco: full support for tile buffer eot handling 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
59dc07e02c pco: improve image write using pck.prog 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:12 +00:00
Simon Perretta
5fa1bb9194 pvr, pco: alpha to coverage support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
22c67a3c4e pvr, pco: add dummy stores for tilebuffer-only loadops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
297a0c269a pvr, pco: tile buffer support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
de4dd8e9ea pvr, pco: fragment shader metadata boilerplate code 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
78062fbb75 pvr, pco: improved image write (with format) support, handle 111110 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
0c7dc07c93 pvr, pco: add support for gl_FrontFacing 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
ed652e10fc pco: force image/texture array coordinate f2i32 conversions to be rtne 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:11 +00:00
Simon Perretta
0ff8f57392 pvr, pco: simple end-of-tile/render nir shader gen 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
46c9239c11 pvr, pco: initial texture gather support with gather sampler 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
ac41e9dd18 pco: support combined depth/discard isp feedback 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
0367dc1e42 pco, pvr: sample mask out support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:10 +00:00
Simon Perretta
486ca8bbc1 pvr, pco: basic depth feedback/discard/terminate support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
b50f0b47d2 pco: add support for sscaled8* formats 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
db686e190a pvr, pco: per frag/vertex input/output rework 
Adds support for packing and unpacking r10g10b10a2 unorm and
r11g11b10 float formats, as well as partial 2x16 and 4x8 formats.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00
Simon Perretta
3af73ef199 pco: initial image support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36412>
 2025-09-16 18:26:09 +00:00