There are two "shapes" of TEXC in the IR:
* Regular texturing. This TEXC writes a single set of staging registers.
* Dual texturing. This TEXC writes two sets of staging registers.
Currently we model both with a 2-destination TEXC, with a null second
destination for the usual case where dual texturing isn't used. This is awkward.
To make the "shapes" of instructions more predictable, make TEXC only write a
single set of staging registers (like the hardware instruction) and split off a
TEXC_DUAL pseudoinstruction for the second case, lowered late.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
This ensures the shape of the split is correct (no nulls in the destination).
This should not affect the register allocation, though it does "cost" extra
variable names.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Removing dests without removing instructions only makes sense for certain
pseudo-instructions, but it makes the IR needlessly complicated for all
instructions. There's no real reason to do so, we can signal this in a different
way instead.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
On Bifrost, BLEND writes to the link register, acting like a function call. On
Valhall, BLEND does not write anything. But the BLEND instruction in our IR is a
pseudo-instruction with Bifrost semantics, expanding to a multi-instruction
sequence on Valhall. So it's not worth special casing Valhall in instruction
selection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Use "r0" style to denote machine registers, consistent with the assembly. Use
instead "nr0" for NIR registers so they don't collide. This reduces noise for
the average case (either register allocated or almost SSA).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Now we can trust in I->nr_dests, avoiding a bunch of special cases and incorrect
printing for instructions without a destination. To compensate for those
instructions being hard to scan now, indent.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Now that we set nr_srcs/nr_dests accurately, assert as much in the validator.
This pass will be deleted later in the series, but having it here is expected to
be useful for bisection, in case there are cases missed. Certainly running the
CTS at this point in the series is helpful to prove completeness of the
beginning of this series.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
ATEST on Valhall takes atest-param as an explicit encoded source. The source
also exists on Bifrost, but it's implied in the encoding. Rather than treating
it as a "ghost" source, model it in the IR explicitly so the count is correct.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
The builder is the primary producer of instructions, and generally the shape of
an instruction is fixed at build-time. It must set nr_dests/nr_srcs
appropriately. Likewise, when we modify sources later, we need to update
nr_srcs/nr_dests to keep everything consistent (and keep the tests passing).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
The different combine modes form different instructions from each other and in
particular from the two-source version on Bifrost. Model them as such so we can
represent the relevant Valhall-specific lowering/optimizations accurately in the
compiler.
This requires updating the unit tests to use the new names since there's not
much point keeping around the aliases.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
Valhall-style comparisons are 3-source, allowing multiple comparisons to be
combined without bitwise arithmetic. For example, the sequence
FCMP.f32.eq t, z, w
FCMP_AND.f32.eq dest, x, y, t
calculates (z == w) && (y == t) in 2 instructions (would be 3 on Bifrost).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
If an instruction has multiple destinations and *any* of them are needed by
helper invocations, we should keep helper invocations alive. This is a bug fix.
Consider the GLSL:
first = texture(sampler, ...);
float res = texture(sampler, vec2(first.y)).x + first.x;
Corresponding to the IR:
first = ...
x, y, z, w = SPLIT first
second = TEX y, y
x', y', z', w' = SPLIT second
FADD res, x, x'
Here, x is not required by helper invocations (the coordinates to TEX) while y
is required. If we only look at only the first destinations, we incorrectly
decide that first is not required and fail to set the .skip bit, leading to
incorrect results.
Fixes: 5febeae58e ("pan/bi: Emit collect and split")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
...with dual source blending. Fixes shaders/dolphin/smg.1.shader_test
There are more IR sources than Valhall machine sources here.
Fixes: b48933d641 ("pan/va: Include BLEND for va_swap_12")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17794>
../../src/gallium/auxiliary/hud/hud_context.c:1017:1: error: static declaration of 'access' follows non-static declaration
These error will shown when any header #include <io.h>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18333>
The GLSL code sequence:
texture2D(tex0, u_coords) + texture2D(tex1, u_coords)
will be optimized to
TEXC_DUAL tex0/tex1, u_coords, #texture_descriptor
If this optimization happens after lowering FAU, the resulting TEXC instruction
is unschedulable: both the uniform and the constant descriptor fight for the
same FAU slot.
However, if this optimization happens before lowering FAU, then the FAU lowering
will move the descriptor into a register, complicating the dual texturing fixup
in RA.
To fix this interaction, fuse dual texturing before lowering FAU and keep
texture descriptors as constants when lowering FAU of TEXC.
Fixes scheduling failure in piglit drawoverhead -test 3 with uniform reordering.
Fixes: a4d3a29647 ("pan/bi: Enable dual texture fusing pass")
Fixes: 6b2eda6b72 ("pan/bi: Reorder pushed uniforms to avoid moves")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18378>
If we're using the blit-path, we don't update the compressed image, which
will be needed if an application try to download the texture-image again
afterwards.
I previously fixed this for the memcpy-codepath, but we actually need to
fall back for the blit code-path as well. So let's move this early-out
earlier to catch both.
Fixes: 8f446322e1 ("mesa/st: do not use memcpy when using compressed fallback")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18342>
We don't want to print out too many :
MESA: error: ../src/intel/vulkan/anv_device.c:769: anv does not support Intel(R) HD Graphics (HSW GT1); use hasvk (VK_ERROR_INCOMPATIBLE_DRIVER)
whenever anv is not able to load on a HSW device. Similarly hasvk
should not print error on anything gfx9+.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
We don't need the relocation offsets anymore, and just want to pin the
BO, and combine the address into a uint64_t. We can just open code
those two things; it's actually less code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
We don't need the offset to write a relocation at any longer, so all
it does is call anv_reloc_list_add_bo() at this point. Just use that.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
We now always softpin and use the load_global_constant case, so there's
no need to set up a UBO for NIR constants.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
This was only needed on Haswell and older due to the kernel command
parser not allowing us to chain batches. anv no longer support this.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18208>
