Commit graph

91 commits

Author SHA1 Message Date
Nanley Chery
dfcd93d12f intel/isl: Fix packing of SINT formats
Prevents the next patch from failing many multisampled, signed integer
rendering tests. For example:

 dEQP-VK.renderpass2.suballocation.multisample_resolve.r8_sint.samples_4

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30646>
2024-08-23 15:28:34 +00:00
Jianxun Zhang
255889a795 isl: Remove restriction of CCS_E support on formats (xe2)
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
2024-06-26 05:25:43 +00:00
Tapani Pälli
4a0a716b6a isl: fix condition for enabling sampler route to lsc
This will disable cases with 2D array views (which could be views to 3D
texture) but enables on regular 2D surfaces which seems to work fine.

Fixes: 70382f7f06 ("intel/isl/xe2: Enable route of Sampler LD message to LSC")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29760>
2024-06-24 09:23:07 +00:00
José Roberto de Souza
475661a64e intel/isl/xe2: Disable route of Sampler LD message to LSC
This optimization is causing some tests groups to fail, like:
dEQP-VK.image.mutable.2d_array.*
dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.*

So disabling it until properly fixed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27016>
2024-01-12 01:51:59 +00:00
Mark Janes
590fe58ef6 intel: remove MTL a0 workarounds
Meteorlake shipped with the b0 stepping.  Remove fixes for hardware
bugs that were corrected prior to the platform release.

Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26898>
2024-01-05 22:51:46 +00:00
José Roberto de Souza
70382f7f06 intel/isl/xe2: Enable route of Sampler LD message to LSC
Xe2 allows route of LD messages from Sampler to LSC to improve
performance when some restrictions are met.

BSpec: 57023
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26801>
2024-01-02 21:14:42 +00:00
Sagar Ghuge
9d7166dfc0 isl: Use 16-bit instead of 8-bits for surface format info fields
Comparing uint8_t max value 255 with devinfo->verx10 will work fine for
now but for future platforms, comparison will fail. To avoid this
let's switch the field data type from 8-bits to 16-bits.

v1: (Jordan)
- Use 16 bits instead of 32 and add assertion.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25478>
2023-10-02 17:24:33 +00:00
José Roberto de Souza
f7e39c6f85 intel/isl: Remove Wa_22011186057
This is a ADL-P workaround of a pre-production stepping, with RPL-P
already being sold we can remove this workaround.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24699>
2023-08-15 18:47:36 +00:00
Yonggang Luo
86bcc90c0e intel/compiler,intel/blorp,intel/vulkan: decouple vulkan driver and compiler from gallium
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24438>
2023-08-03 22:00:15 +00:00
Jordan Justen
dbf19b76e8 intel/isl: Use intel_needs_workaround() for MTL CCS WA
Also use parent WA number of 14017240301 instead of 14017353530.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22401>
2023-07-28 15:23:47 -07:00
Sviatoslav Peleshko
0ed8a48ce9 isl: Check all channels in isl_formats_have_same_bits_per_channel
Cc: 22.2 <mesa-stable>
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
2023-04-27 01:04:44 +00:00
Lionel Landwerlin
d4f498a583 isl: fix a number of errors on storage format support on Gfx9/12.5
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22302>
2023-04-18 08:38:55 +00:00
Rohan Garg
80790f50db isl: fix some documentation
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21283>
2023-02-14 16:55:21 +00:00
Jordan Justen
5df50292d6 intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20322>
2022-12-15 11:43:00 -08:00
Nanley Chery
e4e4ba2304 intel: Allow CCS_E on R11G11B10_FLOAT for TGL+
We now support blorp_copy with this format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
2022-12-14 03:05:24 +00:00
Nanley Chery
e862626031 intel/isl: Bump format_info entries from 100 to 110
The new format support is only tested on Ice Lake and onward. Makes the
next patch clearer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
2022-12-14 03:05:24 +00:00
Nanley Chery
2b2141d193 intel/isl: Lessen CCS_E-compatibility checks for TGL+
Tiger Lake and onward allow drivers to specify a compression format
independently from the surface format. So, even if the surface format
changes, hardware is still able to determine how to access the CCS.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jianxun Zhang <jianxun.zhang@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19937>
2022-12-14 03:05:24 +00:00
Jordan Justen
4db33adf9d intel/isl: Disable CCS on MTL
MTL requires some ccs/aux-map changes from Jianxun Zhang, which are
still in progress. So, for now we disable ccs on MTL.

Rework:
 * Drop change in isl_surf_supports_ccs (Nanley)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20046>
2022-11-28 17:09:52 -08:00
Lionel Landwerlin
ab4beaf3fb isl: add new helper for format component compatibility
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17329>
2022-07-11 14:57:26 +00:00
Jason Ekstrand
bc5e77a9f2 isl: Use util_sign_extend
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214>
2022-07-06 11:23:18 +00:00
Kenneth Graunke
f052e00a58 isl: Add an isl_format_supports_typed_atomics() helper.
v2: Add a fields in isl_format with per gen support (Lionel)

v3: Fixup R32_FLOAT from 80 to 90
    Fixup R32_[SU]INT from 80 to 70 (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14712>
2022-06-01 10:05:19 +00:00
Nanley Chery
cc973de5f6 intel/isl: Support YUV pipe-to-isl format mapping
This will help to configure surfaces for media compression.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14355>
2022-01-28 00:30:55 +00:00
Nanley Chery
531b1b7511 intel/isl: Strengthen MCS SINT format restriction
The gfx7 MCS restriction for SINT formats actually applies to
multisampling in general. Place the stronger restriction in the format
support check and assert this in isl_surf_get_mcs_surf.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14464>
2022-01-21 20:38:05 +00:00
Dave Airlie
d051854cca treewide: drop mtypes/macros includes from main
These aren't required in lots of places, so remove them.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127>
2021-12-08 22:14:45 +00:00
Nanley Chery
0e075227d8 intel/isl: Restore CCS_E support for YUYV and UYVY
These formats are used when creating surfaces with the
I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS modifier.

Makes iris pass the out-of-tree piglit test,
ext_image_dma_buf_import-intel-modifiers.

Fixes: 1433fe7860 ("intel/isl: Unify fmt checks in isl_surf_supports_ccs")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14082>
2021-12-07 23:31:23 +00:00
Nanley Chery
1433fe7860 intel/isl: Unify fmt checks in isl_surf_supports_ccs
On TGL+, require that the surface format supports CCS_E in order to
support CCS. This aligns with the ISL code that pads the primary
surface for CCS on this platform.

Pre-TGL, require support for either CCS_D or CCS_E.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12398>
2021-12-01 20:36:38 +00:00
Lionel Landwerlin
361b3fee3c intel: move away from booleans to identify platforms
v2: Drop changes around GFX_VERx10 == 75 (Luis)

v3: Replace
   (GFX_VERx10 < 75 && devinfo->platform != INTEL_PLATFORM_BYT)
   by
   (devinfo->platform == INTEL_PLATFORM_IVB)
   Replace
   (devinfo->ver >= 5 || devinfo->platform == INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 >= 45)
   Replace
   (devinfo->platform != INTEL_PLATFORM_G4X)
   by
   (devinfo->verx10 != 45)

v4: Fix crocus typo

v5: Rebase

v6: Add GFX3, ILK & I965 platforms (Jordan)
    Move ifdef to code expressions (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12981>
2021-11-08 16:48:06 +00:00
Tapani Pälli
70f193ffcf intel/isl: FXT1 support was removed on Gfx12.5
v2: cleanup (Jordan Justen)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13241>
2021-10-08 15:45:21 +00:00
Jason Ekstrand
e7f3da0138 intel/isl: ASTC support was removed on Gfx12.5
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Jason Ekstrand
8afc9626ad intel/isl: Stop claiming ASTC works on Cherry View
We do, however, leave a nice tombstone comment in case anyone comes
looking.  Given the age and scarcity of Cherry View hardware and ASTC
apps that run on desktop Linux, it's unlikely we'll ever bother to
implement it.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Jason Ekstrand
0c618f308c intel/isl: Simplify isl_format_supports_filtering
For compressed formats, filtering and sampling has always gone together.
This lets us avoid duplicating all those nasty special cases between the
two functions.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>
2021-10-06 15:04:33 +00:00
Ian Romanick
9dfe7fbc6b isl: Use CLAMP macro instead of MIN of MAX
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:11 -07:00
Ian Romanick
72259a870f util: Add and use functions to calculate min and max int for a size
Many places need to know the maximum or minimum possible value for a
given size integer... so everyone just open-codes their favorite
version.  There is some potential to hit either undefined or
implementation-defined behavior, so having one version that Just Works
seems beneficial.

v2: Fix copy-and-pasted bug (INT64_MAX instead of INT64_MIN) in
u_intmin.  Noticed by CI.  Lol.  Rename functions
`s/u_(uint|int)(min|max)/u_\1N_\2/g`.  Suggested by Jason.  Add some
unit tests that would have caught the copy-and-paste bug before wasting
CI time.  Change the implementation of u_intN_min to use the same
pattern as stdint.h.  This avoids the integer division.  Noticed by
Jason.

v3: Add changes to convert_clear_color
(src/gallium/drivers/iris/iris_clear.c).  Suggested by Nanley.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12177>
2021-08-03 12:55:02 -07:00
Ian Romanick
3fa16b3025 intel/isl: Add mappings for PIPE_FORMAT_R8G8_R8B8_UNORM and PIPE_FORMAT_G8R8_B8R8_UNORM
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
2021-05-21 01:40:22 +00:00
Marcin Ślusarz
7e6a7dba1e intel/isl: replace format_gen by verx10
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
2021-05-17 09:46:45 +00:00
Jordan Justen
89f3312625 intel/isl: Add Wa_22011186057 to disable CCS on ADL GT2 A0
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9465>
2021-05-14 06:10:47 +00:00
Lionel Landwerlin
df0580312a isl: document format fields
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
2021-05-05 12:20:09 +00:00
Jason Ekstrand
b80720acb1 intel/isl: Fix isl_color_value_unpack to match the prototype
The prototype uses a pointer and the actual function definition had an
array.  For some reason, GCC never complained about this until GCC 11.
This fixes a compile warning when building with GCC 11.

Fixes: 09ced65420 "intel/isl: Add format conversion code"
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10537>
2021-04-30 17:01:05 +00:00
Anuj Phogat
61e8636557 intel: Rename gen_device prefix to intel_device
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
2021-04-20 20:06:33 +00:00
Anuj Phogat
cd39d3b1ad intel: Rename gen_device prefix in filenames
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
find $SEARCH_PATH -type f -name "gen_device" -exec sh -c 'f="{}"; mv -- "$f" "${f/gen_device/intel_device}"' \;
grep -E "gen_device_info*\.[cph]" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device_info\(.*\.[cph]\)/intel_device_info\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
2021-04-20 20:06:33 +00:00
Anuj Phogat
1d296484b4 intel: Rename Genx keyword to Gfxx
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "Gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/Gen\([[:digit:]]\+\)/Gfx\1/g"

Exclude changes in src/intel/perf/oa-*.xml:
find src/intel/perf -type f \( -name "*.xml" \) | xargs sed -ie "s/Gfx/Gen/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
b75f095bc7 intel: Rename genx keyword to gfxx in source files
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat
abe9a71a09 intel: Rename gen field in gen_device_info struct to ver
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Nanley Chery
5e27e04322 intel/isl: Drop redundant unpack of unorm channels
Fixes: 09ced65420 ("intel/isl: Add format conversion code")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7168>
2020-10-16 18:35:57 +00:00
Sagar Ghuge
3547e19bbd intel/isl: Switch to R8_UNORM format for compatiblity
Gen12 added CCS_E support for A8_UNORM. Intercept A8_UNORM format and
switch to R8_UNORM, as both share the same aux map format encoding so
they are compatible.

Fixes Piglit's ext_framebuffer_multisample-formats all_samples, which
was hitting an assert about A8_UNORM and R8_UINT not being CCS_E
compatible formats.

v2: Add gen check (Kenneth Graunke)

v3: Intercept A8_UNORM and set format to R8_UNORM (Jason Ekstrand)

v4:
- Remove gen check and move block little bit down (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
2020-02-13 18:44:50 +00:00
Eric Anholt
5bea0cf779 intel/isl: Move iris's pipe-to-isl format function to isl.
This will get reused in the shader compiler once we switch it over to pipe
formats instead of GL enums.  We can't easily deduplicate i965's
mesa-to-isl mapping because of cases like A32_FLOAT that are mapped
differently.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3355>
2020-02-05 10:31:09 -08:00
Jason Ekstrand
4d03e53127 intel/isl: Allow CCS_E on more formats
Now that BLORP supports copies on everything except R11G11B10_FLOAT,
we should be able to support CCS_E those formats.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3554>
2020-01-25 17:48:54 +00:00
Nanley Chery
6670e07a6e intel: Enable CCS_E for R24_UNORM_X8_TYPELESS on TGL+
While this format isn't listed in BSpec: 53911, other documentation and
empirical evidence suggest that it's fine to remap it to R32_FLOAT. I've
filed a bug for the BSpec page.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28 10:47:05 -07:00
Nanley Chery
e655eed531 intel: Enable CCS_E for some formats on Gen12
In ISL:
   Update the format table to add CCS_E support for some 8BPP formats,
   some 16BPP formats, and R10G10B10A2_UNORM_SRGB.

   In the helper for determining CCS_E support, we return false for some
   16BPP formats because they aren't properly handled in blorp_copy().

In BLORP:
   Allow the new and non-problematic formats for CCS_E-enabled copies.

v2. Update other fields for A1B5G5R5_UNORM and A4B4G4R4_UNORM in table.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
2019-10-28 10:47:05 -07:00
Nanley Chery
a94cb6503f isl: Disable CCS_D on Gen12+
Clear-only compression no longer exists on TGL.

v2. Add BSpec reference. (Sagar)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-28 10:47:04 -07:00