Commit graph

47736 commits

Author SHA1 Message Date
Marek Olšák
2272db2ac6 radeonsi: set the valid buffer range for bindless image buffers
This was missing.

Cc: mesa-stable

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31651>
2024-10-16 00:27:56 +00:00
Karol Herbst
ff2c4e8f11 zink: add CL CTS result
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31614>
2024-10-15 21:07:07 +00:00
Pavel Ondračka
58d6906f8c r300/ci: update ci expectations after piglit uprev
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31663>
2024-10-15 17:43:00 +00:00
Aleksi Sapon
ad4635d6ef llvmpipe: implement alpha-to-coverage dithering
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31373>
2024-10-15 16:17:40 +00:00
Deborah Brouwer
0007077c11 ci: remove xfail program@build@include-directories
Now that build-piglit.sh is no longer removing ‘include_test.h’
this test `program@build@include-directories` is passing which is causing
jobs to fail due to this unexpected improvement. Remove this test from
expected fails so that the jobs can pass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31379>
2024-10-15 15:50:47 +01:00
Collabora's Gfx CI Team
68aa78a858 Uprev Piglit to 7ce69da1199d12ed0ddaa251ed489750523798fb
e9ab30aeae...7ce69da119

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31379>
2024-10-15 15:50:47 +01:00
Mike Blumenkrantz
4ac4004816 llvmpipe: expose GL multiview extensions
this is a no-op since lavapipe is already doing it

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31590>
2024-10-15 14:01:42 +00:00
Mike Blumenkrantz
f5bd39e0e3 gallium: delete duplicated viewmask member in draw info
this was added for lavapipe, but it should have been in the
framebuffer state since it is a framebuffer state

now the GL multiview extensions are supported with viewmask
in the framebuffer struct, which means this is all redundant
and should be corrected/deleted

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31590>
2024-10-15 14:01:42 +00:00
Mike Blumenkrantz
8487ecfa44 iris: assert that viewmask is 0
this is not supported by the driver, so it doesn't need to
be checked at runtime

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31590>
2024-10-15 14:01:42 +00:00
Pavel Ondračka
f94087be2c r300/compiler: reformat using default mesa .clang-format rules
Most notably switch from tabs to 3 spaces.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Acked-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23771>
2024-10-15 09:24:02 +00:00
Pavel Ondračka
4e4b124fa9 r300: add .clang-format file for the compiler
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Acked-by: :Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23771>
2024-10-15 09:24:02 +00:00
Pavel Ondračka
0a81dc8782 r300/ci: add deqp and piglit on RV410
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30137>
2024-10-14 17:25:53 +00:00
Pavel Ondračka
bb3eb60c0c r300/ci: share some common variables
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30137>
2024-10-14 17:25:53 +00:00
Christian Gmeiner
63f0a2f9a0 vc4: Add a few function traces
Sprinkle around a few traces that were useful in locating submit and
fence waits.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31575>
2024-10-14 12:21:51 +00:00
Christian Gmeiner
cf939334e6 v3d: Add a few function traces
Sprinkle around a few traces that were useful in locating submit and
fence waits.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31575>
2024-10-14 12:21:51 +00:00
Rob Clark
c7b126f627 freedreno: Balance out u_blitter cb0 save/restore
Fixes: 5de33f3d3e ("freedreno: Implement stencil blit fallback")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31569>
2024-10-13 15:18:40 +00:00
Pavel Ondračka
cc14d40239 r300: remove gl_ClipVertex early
There is no HW support, but in some cases the shaders mostly work even
if we ignore it, and so far we have just done so. However since the
driver didn't know to what output position in the PVS we should
redirect it, it ended in the first slot. Importantly, if the
CLIP_VERTEX output would be written after position (which actually
belongs in the first slot) it would overwrite it and things blow up.

So just remove it early, and also improve the warning a bit, including
the part that we could use draw module to actually emulate the feature.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11856
Fixes: 5dcef1e7b8
Reviewed-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31547>
2024-10-13 05:47:17 +00:00
GKraats
a2b97b7b56 i915g: fix GL_TEXTURE_BASE_LEVEL MAX_LEVEL MIN_LOD and MAX_LOD
Since opengl 1.4 i915g should support GL_TEXTURE_BASE_LEVEL,
GL_TEXTURE_MAX_LEVEL, GL_TEXTURE_MIN_LOD and GL_TEXTURE_MAX_LOD.
This MR fixes it.
See also check at tests/texturing/tex-miplevel-selection.c at piglit.

Signed-off-by: GKraats <vd.kraats@hccnet.nl>
Tested-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31073>
2024-10-12 23:38:04 +00:00
David Rosca
6a598cccc3 radeonsi/vcn: Select layer for rate control
This makes the per-layer rate control work. Previously it would always
use rate control params for last configured layer.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31148>
2024-10-11 13:55:54 +00:00
David Rosca
d2ad188915 radeonsi/vcn: Implement per-layer rate control for HEVC
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31148>
2024-10-11 13:55:54 +00:00
David Rosca
ce2eedd13e frontends/va: Fix parsing HEVC st_ref_pic_set
According to spec, the slice ref pic set is the last entry
in st_ref_pic_set[] array.
As such, the maximum number of st ref pic sets is 65.

Fixes: ef8ba75718 ("frontends/va: Parse HEVC slice packed header")

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31308>
2024-10-11 10:46:49 +00:00
Christian Gmeiner
babeba264b etnaviv: Implement ARB_draw_indirect
Passes all relevant piglits with forced GLSL 330 and GL 3.1.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31535>
2024-10-11 07:42:47 +02:00
Karol Herbst
767695b2c4 asahi: implement get_cl_cts_version
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31589>
2024-10-10 18:24:31 +00:00
Jose Maria Casanova Crespo
687ed3fcaa v3d: initialize job local key with the 8 color buffer available in v7.1+
Fixes: 9e90d95508 ("v3d,v3dv: support up to 8 render targets in v7.1+")

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31582>
2024-10-10 16:44:58 +00:00
Daniel Stone
3e7c9aad8a ci/virgl: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL/Vulkan at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
4e3e84c240 ci/zink: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
61f5178f6e ci/swrast: Archive Xvfb logs
If anything goes wrong, it's useful to have actual output, as opposed to
guessing from the void.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
8b594d29b6 ci/swrast: Fix library paths for llvmpipe/softpipe
We need to set $LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI
modules. We were setting $LD_LIBRARY_PATH, but llvmpipe was getting it
wrong, so Weston was picking up the host GLES, which we're about to no
longer install.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Erik Faye-Lund
cf71e5534b i915: do not calculate native instructions
This isn't wired up anywhere, so let's just drop it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31538>
2024-10-10 09:36:43 +00:00
David Rosca
3c5fe03b92 radeonsi/vcn: Add support for VCN5 dpb tier2
Co-authored-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
1e1f078099 radeonsi/vcn: Add support for VCN5 AV1 compound
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
05f7589fec radeonsi/vcn: Fix coded size in sequence header on VCN5
Introduce coded_width/coded_height for values used in headers
and change it to aligned size on VCN4 to reflect the actual coded size.
VCN5 doesn't have this limitation and can code any size.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
8b2f0fb574 radeonsi/vcn: Support raw packed headers for AV1
Same as H264/HEVC, we still write sequence header ourselves
and slice header is sent to FW, everything else gets copied
directly to output bitstream buffer.
Fixes generating correct output with libva-utils/av1encode.
Also fixes temporal delimiter insertion, it's no longer forced
on every frame, but instead it lets application handle it.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
813812b925 radeonsi/vcn: Switch to app DPB management for AV1
Also move the common part of the frame header into shared function.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
Christian Gmeiner
3ae3425c5d etnaviv: blt: Convert assert to real if
etna_try_blt_blit(..) returns if it is possible to do the blit
in hardware or not. When building mesa in debug mode this assert(..)
is hit many times.

Fixes the following piglits on GC7000L:
 - spec@!opengl 1.0@gl-1.0-scissor-copypixels
 - spec@nv_conditional_render@copypixels
 - spec@!opengl 1.1@copypixels-draw-sync
 - spec@!opengl 1.1@copypixels-sync
 - spec@!opengl 1.1@depthstencil-default_fb-blit
 - spec@!opengl 1.1@draw-copypixels-sync
 - spec@!opengl 1.1@gl-1.1-xor-copypixels

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31581>
2024-10-10 08:31:53 +00:00
David Rosca
20d5020ad7 radeonsi/vcn: Fix out of bounds read in H264 decode
When all 16 references are used, this would read pic->ref[16].
Same for HEVC, but HEVC only uses 15 reference frames so it would
never happen there yet is still reported by coverity.

Fixes coverity issues 1497283 and 1465569 Out-of-bounds read

Cc: mesa-stable

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:36 +00:00
David Rosca
10a7356488 radeonsi/vcn: Fix out of bounds write when invalidating QP map regions
Fixes coverity issue 1559460 Out-of-bounds write

Fixes: 9c07a2e10d ("radeonsi/vcn: ROI feature implementation")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
David Rosca
17842f0584 radeonsi/vcn: Fix some small coverity issues
* 1619409 Resource leak
  - fix leak when mapping encode bitstream buffer fails
* 1619403 Dereference after null check
  - remove size ptr NULL check in radeon_enc_get_feedback, can't be NULL
* 1434887 Out-of-bounds access
  - use correct variable for memset in get_vp9_msg
* 1619400 'Constant' variable guards dead code
  - remove code handling frame_mbs_only_flag == 0, hardcoded to true

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
Guilherme Gallo
59d909eb56 ci/lava: Make perf jobs use pyutils artifact
Following the merge of Merge Request #31151, we encountered an issue
where the performance jobs were failing silently. Although these
failures did not cause the pipeline to fail, they resulted in warnings
for all merge requests that ran the .*-traces-performance jobs, putting
critical performance data for the [Mesa Performance Driver
dashboard](https://ci-stats-grafana.freedesktop.org/goto/G3xkvykHg?orgId=1)
at risk.

To resolve this issue, this commit updates the LAVA performance jobs to
utilize the Pyutils artifact package, which is now the only required
artifact for the jobs that run the LAVA job submitter.

Fixes: dd5d737e6c ("ci/lava: Use new pyutils container")

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31553>
2024-10-10 01:33:16 +00:00
Rob Clark
753c8bf834 freedreno/a6xx: Emit CP_SET_AMBLE packets
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
d572fcf04a freedreno/a6xx: Move more state emit per-bin
With skipsaverestore=1 we can't rely on this values being restored.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
270e595811 freedreno/a6xx: Move static regs to preamble IB
We can re-use this for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
0c36ca7446 freedreno/a6xx: Move PC_TESSFACTOR_ADDR emit
This depends on batch state, so emit in gmem code.  The remainder of the
static reg initialization can be re-used across batches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
f3cc9335e6 freedreno/a6xx: Set bin size per bin
It is not saved/restored by level 1 preemption with skipsaverestore=1,
so we need to set it for each bin.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
be6342633c freedreno/a6xx: Cleanup WFIs around RB_CCU_CNTL
This was only actually needed on the earliest a6xx (probably just
a630?).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
3aac51a6d5 freedreno/a6xx: De-open-code VFD_MODE_CNTL
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
2f82555efa freedreno/a6xx: Only emit VFD/PC_POWER_CNTL for a6xx
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Jonathan Marek
b6432a6c66 freedreno/a6xx: add missing USES_GMEM flag and BIN_RENDER_END markers
Add USES_GMEM flag to indicate that GMEM is in use, so that preemption can
know it needs save and restore GMEM contents.

The missing BIN_RENDER_END markers are also added, their purpose is to
clear the USES_GMEM flag once GMEM is no longer in use.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Jonathan Marek
72900e1aac freedreno: improve a6xx CP_SET_MARKER xml definition
Use real names for most of a6xx_marker enum, add USES_GMEM, remove
overlapping bitfields.

Note the actual "real names" start with PM4_RENDER_MODE_ instead of RM6_

This is a small change to adreno_pm4.xml, with the corresponding
find/replace and updated ci references

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Lionel Landwerlin
e4d1fd7fd6 iris: delete stencil mapping support
Now that we have ISL support.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00