Commit graph

7688 commits

Author SHA1 Message Date
Rhys Perry
a9562fd0d6 aco: fix validation of DPP v_cndmask_b32/v_addc_co_u32
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11924>
2021-08-19 18:17:33 +00:00
Samuel Pitoiset
ab35a63dea radv: do not allocate the FCE predicate for images that use comp-to-single
Images that support comp-to-single don't have to be fast-cleared at
all, so the predicate is unnecessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12323>
2021-08-19 07:50:50 +00:00
Samuel Pitoiset
ef546cf96f radv: remove useless check about the FCE predicate offset
radv_update_fce_metadata() already prevents that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12323>
2021-08-19 07:50:50 +00:00
Samuel Pitoiset
dc58b0112f radv: determine if an image support comp-to-single at creation time
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12323>
2021-08-19 07:50:49 +00:00
Samuel Pitoiset
b16f3261a7 radv: fix fast clearing depth images with mips on GFX10+
Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12325>
2021-08-18 08:27:32 +02:00
Jason Ekstrand
48e8efd00e vulkan,radv: Move vk_format_depth/stencil_only to common code
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
2021-08-17 21:29:35 +00:00
Jason Ekstrand
7878d516c6 radv: Add asserts to vk_format_depth/stencil_only
It doesn't make sense to ask for the depth-only or stencil-only format
if there is no depth or stencil.  One bit of radv_image.c did seem to
take advantage of the default case in vk_format_depth_only so throw an
`if (vk_format_has_depth(format))` around it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
2021-08-17 21:29:35 +00:00
Bas Nieuwenhuizen
3b00696117 radv: Check format before calling depth_only/stencil_only.
Breaks when we drop the fallback in those functions.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
2021-08-17 21:29:35 +00:00
Filip Gawin
46d0126deb radv: improve rounding of zmin
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12388>
2021-08-17 11:03:59 +00:00
Samuel Pitoiset
80e5e059fa radv: fix pre-computing viewport xform when setting new viewports
viewportCount is the number of viewports in pViewports while
firstViewport is the index.

Fixes new CTS dEQP-VK.draw.depth_clamp.*_clamp_four_viewports

Fixes: a2ef92d7a5 ("radv: pre-calculate viewport transforms")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12353>
2021-08-17 08:20:02 +02:00
Eric Engestrom
f1eae2f8bb python: drop python2 support
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3674>
2021-08-14 21:44:32 +00:00
Michel Zou
e4c0a34bfe radv: fix build with mingw
Cc: 21.2 mesa-stable
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

Closes #5092

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12178>
2021-08-13 12:13:21 +02:00
Rhys Perry
c14a85e756 radv: enable DCC with signedness reinterpretation
It seems we can enable DCC if the possible formats differ in signedness
and are otherwise compatible. We just need a fast-clear eliminate for
certain clear colors.

Improves Trine 4 performance.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9387>
2021-08-12 17:14:00 +01:00
Samuel Pitoiset
96403c1ec4 radv: allow fast clears for concurrent images if comp-to-single is supported
Only GFX10+ is affected because older chips don't support
comp-to-single. For them, we need to implement FCE on compute with DCC
and eventually CMASK.

Fixes the gap between concurrent vs exclusive queue with Scarlet Nexus,
also gives a boost with Doom Eternal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12088>
2021-08-10 12:52:14 +02:00
Samuel Pitoiset
7ccecf2096 radv: enable DCC fast-clears with comp-to-single on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
aafe73561e radv: skip FCE for images that are fast-cleared using comp-to-single
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
7451eb1d61 radv: implement DCC fast clears with comp-to-single
When an image supports comp-to-single, DCC is cleared to 0x10 (single)
and the clear color value is written to the beginning of each 256B
block in the image.

This allows to skip FCE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
782e0d05b0 radv: determine if an image support fast clears using comp-to-single
Only on GFX10+ with DCC enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
c336c4b0cb radv: add RADV_DCC_CLEAR_SINGLE
When DCC is cleared with that code, the hardware expects the clear
color value to be stored at the beginning of each 256B block in
the image.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
6b1afe33b2 radv: pass an image view to vi_get_fast_clear_parameters()
image_format was unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
139d34d657 radv: use more explicit DCC clear codes
No functional changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10518>
2021-08-10 08:20:17 +00:00
Samuel Pitoiset
deecc7d109 radv: fix reported sample counts for VRS 1x1
The Vulkan spec requires ~0 for 1x1.

Fixes dEQP-VK.fragment_shading_rate.misc.shading_rates.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12245>
2021-08-10 07:24:22 +00:00
Samuel Pitoiset
1a7eb424b0 radv: bump maxFragmentShadingRateCoverageSamples to 32
Minimum required value is 16 but we support up to 32
(2x2 VRS with MSAA 8x).

Fixes dEQP-VK.fragment_shading_rate.misc.limits.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12245>
2021-08-10 07:24:22 +00:00
Samuel Pitoiset
0d605bb8e0 radv: disable fragmentShadingRateWithCustomSampleLocations
From the Vulkan spec 1.2.187.

"fragmentShadingRateWithCustomSampleLocations specifies whether
 custom sample locations are supported for multi-pixel fragments.
 It must be VK_FALSE if VK_EXT_sample_locations is not supported."

VK_EXT_sample_locations is disabled on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12245>
2021-08-10 07:24:22 +00:00
Samuel Pitoiset
e7e8704611 radv: bump maxFragmentSizeAspectRatio to 2
Minimum required value is 2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12245>
2021-08-10 07:24:22 +00:00
Samuel Pitoiset
7ae3881a4b radv: flush caches before performing separate depth/stencil aspect init
It's a RMW operation, also note that DB doesn't use L2 on GFX6-8.

Fixes test_clear_depth_stencil_view() and test_discard_resource() tests
from vkd3d-proton.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12223>
2021-08-09 16:35:41 +00:00
Bas Nieuwenhuizen
02b6015945 radv: Allocate space for inline push constants.
In the compute dispatch path we do not allocate a huge amount
of space to cover everything so the individual functions have to
allocate. This was missing here, causing a hang in Cyberpunk when
accessing the system menu at some locations with thread tracing
enabled.

Fixes: bd1186572f ("radv: add support for push constants inlining when possible")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12271>
2021-08-09 14:26:21 +00:00
Bas Nieuwenhuizen
b2b1e8e40a radv: Use correct signedness in misalign test.
Lots of the MAX2 args end up subtracting two unsigned numbers, which
blows up when the result is negative.

Fixes: 4c99d6ff54 ("radv: flush L2 for images affected by the pipe misaligned issue on GFX10+")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12272>
2021-08-09 14:03:37 +00:00
Samuel Pitoiset
21c8a95e34 radv: remove unnecessary FIXME about custom sample locations
VK_EXT_sample_locations is disabled on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12247>
2021-08-09 11:40:13 +00:00
Samuel Pitoiset
1db36422b9 radv: fix initializing the DS clear metadata value for separate aspects
We shouldn't overwrite the clear value of the other aspect (in case
separate depth/stencil layouts are used).

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12222>
2021-08-09 10:41:39 +00:00
Samuel Pitoiset
ade66c1aeb radv: allow DCC MSAA fast clears if a FCE is needed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
2021-08-09 09:27:52 +00:00
Samuel Pitoiset
f136838d1e radv: perform a FCE for MSAA images that might have been fast-cleared
FMASK_DECOMPRESS can't eliminate DCC fast clears. This will allow to
enable DCC MSAA fast clears that require a FCE.

Only supported on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
2021-08-09 09:27:52 +00:00
Samuel Pitoiset
3cfa3187cb radv: rework DCC, FMASK and FCE decompress path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12180>
2021-08-09 09:27:52 +00:00
Timur Kristóf
74181ffcc5 radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.
The radv_emit_ngg_culling_state function won't write the
SPI_SHADER_PGM_RSRC2_GS register when it knows in advance that
radv_emit_graphics_pipeline will overwrite it anyway.

However, there is an unhandled case:

radv_emit_graphics_pipeline will not emit anything (including this
register) when the pipeline is already emitted. Hence, improve
the check in radv_emit_ngg_culling_state to consider this.

Fixes: 9a95f5487f
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12237>
2021-08-06 12:18:37 +02:00
Rhys Perry
5a536eca9c aco: calculate correct register demand for branch instructions
Since copies for the successor's linear phis are inserted before the
branch, we should consider the definitions and operands of the successor's
linear phis.

Fixes a Detroit: Become Human spilling failure with GCM+GVN.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12035>
2021-08-05 12:01:58 +00:00
Samuel Pitoiset
16793c8efa ac/surface: implement CmaskAddrFromCoord in NIR on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12182>
2021-08-05 06:37:09 +00:00
Samuel Pitoiset
1d67fa4d73 ac/surface: add tests for CmaskAddrFromCoord on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12182>
2021-08-05 06:37:09 +00:00
Samuel Pitoiset
0926b268fc amd/addrlib: expose CMASK address equations to drivers on GFX10+
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12182>
2021-08-05 06:37:09 +00:00
Timur Kristóf
8918a809ce ac: Remove deprecated use_late_alloc field as nobody uses it anymore.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
2021-08-04 15:37:05 +00:00
Timur Kristóf
d911259c3a radv: Use ac_compute_late_alloc in radv_pipeline.
This aligns RADV with RadeonSI in how it handles late alloc,
making it easier for us to deal with deadlocks and such.

Also move setting the RSRC3 registers for VS, GS and NGG
into radv_pipeline.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
2021-08-04 15:37:05 +00:00
Timur Kristóf
61eb3debcf radv: Don't toggle PC oversubscription for NGG culling.
We are going to add this directly to the pipeline.
If a pipeline has such a shader, NGG culling is turned on
most of the time, so it's not useful to toggle this setting.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11905>
2021-08-04 15:37:05 +00:00
Timur Kristóf
448592b9ae aco: Use Navi 10 empty NGG output workaround on NGG culling shaders.
Navi 10 can hang when an NGG workgroup has no output,
so we work around that by always exporting a single zero-area
triangle with a single vertex that has all-NaN coordinates.

Thus far, we only employed this for NGG GS, because on all
other stages, the output can't be empty.

However, with NGG culling, the output can be empty, so let's
apply the same workaround there too.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12169>
2021-08-04 12:28:34 +00:00
Rhys Perry
566970f273 aco: use image_dim and image_array intrinsic indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12190>
2021-08-04 12:09:07 +00:00
Rhys Perry
39db5a569b radv: set image_dim and image_array intrinsic indices
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12190>
2021-08-04 12:09:07 +00:00
Samuel Pitoiset
ad83c06a5f radv: fix missing cache flushes when clearing HTILE levels on GFX10+
The driver should accumulate the cache flush bits because if it uses
CP DMA for clearing the last level, it won't flush.

Found by inspection.

Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12170>
2021-08-03 12:59:57 +00:00
Samuel Pitoiset
ebea075feb radv: fix selecting the first active CU when profiling with SQTT
Fixes: d26bcc0f5c ("radv: always select the first active CU when profiling with SQTT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12167>
2021-08-03 12:30:41 +00:00
Timothy Arceri
a9ed4538ab nir: add indirect loop unrolling to compiler options
This is where it should be rather than having to pass it into the
optimisation pass every time.

It also allows us to call the loop analysis pass without having to
duplicate these options which we will do later in this series.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12064>
2021-08-03 10:54:50 +00:00
Samuel Pitoiset
a49b397041 ac/surface: implement CmaskAddrFromCoord in NIR
It's similar to DCC, only GFX9 is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
2021-08-03 07:02:48 +00:00
Samuel Pitoiset
eedc0b59b7 ac/surface: copy the CMASK equation to radeon_surf
Only GFX9 is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
2021-08-03 07:02:48 +00:00
Samuel Pitoiset
1f12c3ccc1 ac/surface: store CMASK pitch and height to radeon_surf
Only GFX9+ is currently supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12140>
2021-08-03 07:02:48 +00:00