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radv: Write RSRC2_GS for NGGC when pipeline is dirty but not emitted.

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The radv_emit_ngg_culling_state function won't write the
SPI_SHADER_PGM_RSRC2_GS register when it knows in advance that
radv_emit_graphics_pipeline will overwrite it anyway.

However, there is an unhandled case:

radv_emit_graphics_pipeline will not emit anything (including this
register) when the pipeline is already emitted. Hence, improve
the check in radv_emit_ngg_culling_state to consider this.

Fixes: 9a95f5487f
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12237>
This commit is contained in:
Timur Kristóf 2021-08-06 11:07:54 +02:00
parent 41e093fc98
commit 74181ffcc5
1 changed files with 5 additions and 2 deletions
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7
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -5853,8 +5853,11 @@ radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct rad
rsrc2 = (rsrc2 & C_00B22C_LDS_SIZE) | S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling);
}
/* When the pipeline is dirty, radv_emit_graphics_pipeline will write this register. */
if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)) {
/* When the pipeline is dirty and not yet emitted, don't write it here
* because radv_emit_graphics_pipeline will overwrite this register.
*/
if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) ||
cmd_buffer->state.emitted_pipeline == pipeline) {
radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
}
}